Patents

In this page we list the issued and pending patents and copyrights generated by the researchers of the Nanoscape Lab. Note that the status of a couple of the issued patents are not yet updated in the United States Patent and Trademark Office (USPTO) site.

Issued Patents [Data Obtained from USPTO]

US-20230394122-A1, Multi-layered framework for security of integrated circuits, Inventors: Bhunia; Swarup et al., Publication Date: 12/7/2023, Pages: 24, Granted on: 11/3/2025, [Status not yet updated in USPTO]
US-20250028635-A1, Look-up table-based in-memory computing system, Inventors: Chatterjee; Baibhab et al., Publication Date: 1/23/2025, Pages: 26, Granted on: 10/28/2025, [Status not yet updated in USPTO]
US-12475263-B2, Electromagnetic based secure contact-less integrity verification of hardware and/or software for integrated circuits, Inventors: Bhunia; Swarup et al., Granted on: 11/18/2025, Pages: 29.
US-12470221-B2, Programmable application-specific array for protecting confidentiality and integrity of hardware IPs, Inventors: Swarup Bhunia, Aritra Dasgupta, Pravin Gaikwad, Md Moshiur Rahman, Aritra Bhattacharya, Nij Dorairaj, David Kehlet, Granted on: 11/11/2025, Pages: 49.
US-12329216-B2, System and method for closed-loop active sensing and protection against airborne pathogens, Inventors: Masna; Naren Vikram Raj et al., Publication date: 6/17/2025, Pages: 37.
US-12210663-B2, Decommissioning and erasing entropy in microelectronic systems, Inventors: Bhunia; Swarup et al., Publication date: 1/28/2025, Pages: 22.
US-12123912-B2, Reconfigurable JTAG architecture for implementation of programmable hardware security features in digital designs, Inventors: Bhunia; Swarup et al., Publication date: 10/22/2024, Pages: 20.
US-12118282-B2, Removal of hardware intellectual property and programmable replacement, Inventors: Bhunia; Swarup et al., Publication date: 10/15/2024, Pages: 23.
US-12058238-B2, Predictive joint compression and encryption for images and videos, Inventors: Bhunia; Swarup et al., Publication date: 8/6/2024, Pages: 43.
US-12049151-B2, Multi-level battery systems for battery-operated entities, methods for rapid charge transfer there between, and methods for optimizing entity routing and network charge distribution, Inventors: Wang; Shuo et al., Publication date: 7/30/2024, Pages: 108.
US-12024201-B2, Smart infrastructures and first-responder network for security and safety hazards, Inventors: Chakraborty; Prabuddha et al., Publication date: 7/2/2024, Pages: 30.
US-12026290-B2, Steganography of hardware intellectual property, Inventors: Bhunia; Swarup et al., Publication date: 7/2/2024, Pages: 22.
US-11978023-B2, Drone-based administration of remotely located instruments and gadgets, Inventors: Bhunia; Swarup et al., Publication date: 5/7/2024, Pages: 32.
US-11954201-B2, Framework for obfuscation based watermarking, Inventors: Bhunia; Swarup et al., Publication date: 4/9/2024, Pages: 15.
US-11953548-B2, Invisible scan architecture for secure testing of digital designs, Inventors: Bhunia; Swarup et al., Publication date: 4/9/2024, Pages: 20.
US-11899827-B2, Establishing trust in untrusted IC testing and provisioning environment, Inventors: Bhunia; Swarup et al., Publication date: 2/13/2024, Pages: 23.
US-11890957-B2, System and method for a battery on wheels (BoW) for charging mobile battery-operated units, Inventors: Chakraborty; Prabuddha et al., Publication date: 2/6/2024, Pages: 67.
US-11873214-B2, Nano-electro-mechanical tags for identification and authentication, Inventors: Tabrizian; Roozbeh et al., Publication date: 1/16/2024, Pages: 18.
US-11856096-B2, Defense of JTAG I/O network, Inventors: Bhunia; Swarup et al., Publication date: 12/26/2023, Pages: 24.
US-11797736-B2, SARO: scalable attack-resistant obfuscation of logic circuits, Inventors: Bhunia; Swarup et al., Publication date: 10/24/2023, Pages: 24.
US-11720654-B2, Timed unlocking and locking of hardware intellectual properties, Inventors: Bhunia; Swarup et al., Publication date: 8/8/2023, Pages: 23.
US-11671100-B2, Memory in logic physical unclonable function, Inventors: Bhunia; Swarup et al., Publication date: 6/6/2023, Pages: 24.
US-11657127-B2, Hardware intellectual property protection through provably secure state-space obfuscation, Inventors: Bhunia; Swarup et al., Publication date: 5/23/2023, Pages: 49.
US-11549897-B2, System and method for hand-held NQR-based in-field screening of substances, Inventors: Bhunia; Swarup et al., Publication date: 1/10/2023, Pages: 20.
US-11480614-B2, Side-channel signature based PCB authentication using JTAG architecture and a challenge-response mechanism, Inventors: Bhunia; Swarup et al., Publication date: 10/25/2022, Pages: 32.
US-11419533-B2, Bladder event detection for diagnosis of urinary incontinence or treatment of lower urinary tract dysfunction, Inventors: Damaser; Margot S. et al., Publication date: 8/23/2022, Pages: 26.
US-11376979-B2, System and method for charging a network of mobile battery-operated units on-the-go, Inventors: Chakraborty; Prabuddha et al., Publication date: 7/5/2022, Pages: 66.
US-11341283-B2, Learning guided obfuscation framework for hardware IP protection, Inventors: Alaql; Abdulrahman et al., Publication date: 5/24/2022, Pages: 43.
US-11321510-B2, Systems and methods for machine intelligence based malicious design alteration insertion, Inventors: Bhunia; Swarup et al., Publication date: 5/3/2022, Pages: 28.
US-11314953-B2, Tagging of materials and objects and analysis for authentication thereof, Inventors: Bhunia; Swarup et al., Publication date: 4/26/2022, Pages: 32.
US-11183068-B2, Multi-purpose context-aware bump (CAB) supporting dynamic adaptation of form factors and functionality, Inventors: Bhunia; Swarup et al., Publication date: 11/23/2021, Pages: 17.
US-11144648-B2, Trojan insertion tool, Inventors: Bhunia; Swarup et al., Publication date: 10/12/2021, Pages: 21.
US-11017125-B2, Uniquified FPGA virtualization approach to hardware security, Inventors: Stitt; Greg M. et al., Publication date: 5/25/2021, Pages: 13.
US-10837926-B2, Multi-modal spectroscopic analysis, Inventors: Mandal; Soumyajit et al., Publication date: 11/17/2020, Pages: 19.
US-10586135-B2, Nano-electro-mechanical labels and encoder, Inventors: Tabrizian; Roozbeh et al., Publication date: 3/10/2020, Pages: 9.
US-10521600-B2, Reconfigurable system-on-chip security architecture, Inventors: Bhunia; Swarup et al., Publication date: 12/31/2019, Pages: 18.
US-10478113-B2, Bladder event detection for diagnosis of urinary incontinence or treatment of lower urinary tract dysfunction, Inventors: Damaser; Margot S. et al., Publication date: 11/19/2019, Pages: 26.
US-10283459-B2, Vanishing via for hardware IP protection from reverse engineering, Inventors: Bhunia; Swarup et al., Publication date: 5/7/2019, Pages: 12.
US-10216965-B2, Systems and methods for generating physically unclonable functions from non-volatile memory cells, Inventors: Plusquellic; James et al., Publication date: 2/26/2019, Pages: 25.
US-9685958-B2, Defense against counterfeiting using antifuses, Inventors: Bhunia; Swarup et al., Publication date: 6/20/2017, Pages: 17.
US-9628086-B2, Nanoelectromechanical antifuse and related systems, Inventors: He; Ting et al., Publication date: 4/18/2017, Pages: 16.
US-8402401-B2, Protection of intellectual property cores through a design flow, Inventors: Chakraborty; Rajat Subhra et al., Publication date: 3/19/2013, Pages: 34.
US-7548473-B2, Apparatus and methods for determining memory device faults, Inventors: Chen; Qikai et al., Publication date: 6/16/2009, Pages: 14.
US-7454738-B2, Synthesis approach for active leakage power reduction using dynamic supply gating, Inventors: Bhunia; Swarup et al., Publication date: 11/18/2008, Pages: 30.
US-7319343-B2, Low power scan design and delay fault testing technique using first level supply gating, Inventors: Bhunia; Swarup et al., Publication date: 1/15/2008, Pages: 23.

Published Pending Patents [Data Obtained from USPTO]

US-20250173264-A1, Learning memory systems and methods, Inventors: Bhunia; Swarup et al., Publication Date: 5/29/2025, Pages: 60.
US-20250131234-A1, Systems and methods for interfacing natural intelligence with artificial intelligence, Inventors: Bhunia; Swarup et al., Publication Date: 4/24/2025, Pages: 58.
US-20240335138-A1, IoT-based podiatric activity tracking and recommendation system Inventors: Bhunia; Swarup et al., Publication Date: 10/10/2024, Pages: 31.
US-20240234345-A1, Systems and methods for providing distributed batteries in integrated circuits, Inventors: Bhunia; Swarup et al., Publication Date: 7/11/2024, Pages: 29.
US-20240232491-A1, Apparatus, systems and methods for programmable logic macros, Inventors: Bhunia; Swarup et al., Publication Date: 7/11/2024, Pages: 38.
US-20240201257-A1, Automated test pattern generation for testing design redacting reconfigurable hardware, Inventors: Stitt; Greg M. et al., Publication Date: 6/20/2024, Pages: 24.
US-20240154788-A1, Bitstream initialization for reconfigurable hardware, Inventors: Bhunia; Swarup et al., Publication Date: 5/9/2024, Pages: 22.
US-20230394209-A1, Functional verification flow of obfuscated designs for circuits, Inventors: Bhunia; Swarup et al., Publication Date: 12/7/2023, Pages: 15.
US-20230228815-A1, Invisible scan architecture for secure testing of digital designs, Inventors: Bhunia; Swarup et al., Publication Date: 7/20/2023, Pages: 20.
US-20230029652-A1, Learning-rooted IoT platform, Inventors: Bhunia; Swarup et al., Publication Date: 2/2/2023, Pages: 59.
US-20220374553-A1, Establishing trust in untrusted IC testing and provisioning environment, Inventors: Bhunia; Swarup et al., Publication Date: 11/24/2022, Pages: 23.
US-20220357394-A1, Reconfigurable JTAG architecture for implementation of programmable hardware security features in digital designs, Inventors: Bhunia; Swarup et al., Publication Date: 11/10/2022, Pages: 19.
US-20220253563-A1, Steganography of hardware intellectual property, Inventors: Bhunia; Swarup et al., Publication Date: 8/11/2022, Pages: 21.
US-20220222386-A1, Decommissioning and erasing entropy in microelectronic systems, Inventors: Bhunia; Swarup et al., Publication Date: 7/14/2022, Pages: 22.
US-20220198108-A1, Removal of hardware intellectual property and programmable replacement, Inventors: Bhunia; Swarup et al., Publication Date: 6/23/2022, Pages: 23.
US-20220188387-A1, Timed unlocking and locking of hardware intellectual properties, Inventors: Bhunia; Swarup et al., Publication Date: 6/16/2022, Pages: 23.
US-20220083987-A1, Drone-based administration of remotely located instruments and gadgets, Inventors: Bhunia; Swarup et al., Publication Date: 3/17/2022, Pages: 31.
US-20220077858-A1, Memory in logic physical unclonable function, Inventors: Bhunia; Swarup et al., Publication Date: 3/10/2022, Pages: 24.
US-20220041187-A1, Smart Infrastructures and First-Responder Network for Security and Safety Hazards, Inventors: Chakraborty; Prabuddha et al., Publication Date: 2/10/2022, Pages: 30.
US-20210319101-A1, Framework for obfuscation based watermarking, Inventors: Bhunia; Swarup et al., Publication Date: 10/14/2021, Pages: 14.
US-20210225039-A1, Predictive Joint Compression and Encryption for Images and Videos, Inventors: Bhunia; Swarup et al., Publication Date: 7/22/2021, Pages: 43.
US-20210173963-A1, Learning guided obfuscation framework for hardware IP protection, Inventors: Alaql; Abdulrahman et al., Publication Date: 6/10/2021, Pages: 44.
US-20210148977-A1, Side-channel signature based PCB authentication using JTAG architecture and a challenge-response mechanism, Inventors: Bhunia; Swarup et al., Publication Date: 5/20/2021, Pages: 33.
US-20190305927-A1, Bitstream security based on node locking, Inventors: Bhunia; Swarup et al., Publication Date: 10/3/2019, Pages: 29.
US-20190180041-A1, Reconfigurable system-on-chip security architecture, Inventors: Bhunia; Swarup et al., Publication Date: 6/13/2019, Pages: 18.
US-20190072506-A1, Multi-modal spectroscopic analysis, Inventors: Mandal; Soumyajit et al., Publication Date: 3/7/2019, Pages: 18.

Copyrights

UF# 17542. Copyright, Swarup Bhunia, Prabuddha Chakraborty, Jonathan Cruz, Tamzidul Hoque, “VIPR: A CAD Framework for Machine Learning based Hardware IP Trust Verification,” U.S. Copyright Registration, Disclosure Date Oct. 1. 2018.
UF# 17369. Copyright, Jonathan Cruz and Swarup Bhunia, “SLOT: Statistical Logic Testing for Hardware Trojan Detection”, filed in May 2018, at University of Florida.
UF# 17303. Copyright, Yuanwen Huang, Prabhat Mishra, and Swarup Bhunia, “MERS: Statistical Test Generation for Side-Channel Analysis Based Trojan Detection”, filed in May 2018, at University of Florida.
UF# 17357. Copyright, Jonathan Cruz, Prabhat Mishra, and Swarup Bhunia, “TRIT: Trojan Insertion Tool”, filed in May 2018, at University of Florida.