This project focuses on efficient and reliable AI inference for real-world applications where models must operate under strict constraints on latency, power, and hardware resources, including clinical motor assessment, scientific trigger systems, human-robot collaboration, and intelligent embedded sensing. In these domains, edge deployment is not optional but essential: a Parkinson’s assessment system must process gait data in real time at the point of care, a particle physics trigger system must make decisions in microseconds, a collaborative robot must perceive and react to human intent with zero tolerance for latency, and an embedded platform must sustain intelligent perception without cloud access or abundant power.
To meet these demands, we develop compression and acceleration pipelines that treat model design and hardware implementation as a unified co-design problem. At the heart of this approach is the use of Field Programmable Gate Arrays (FPGAs), reconfigurable chips that can be tailored in software to match the exact computational structure of a target model. Quantization, knowledge distillation, and pruning decisions are grounded in what the target hardware can actually support, so that compression translates into verified real-device performance and not just theoretical efficiency. In human-robot collaboration specifically, onboard FPGA inference eliminates offloading latency and privacy concerns while keeping robots responsive and safe in shared human spaces.
The overarching goal is to close the gap between algorithmic compression advances and practical deployment realities, delivering low-latency, bit-exact implementations that bring the accuracy of large models to where real-world impact is highest.