Publications

2026

• [DAC’26] Venkata Nithin Kamineni, Habibur Rahaman, Ovishake Sen, Baibhab Chatterjee, Swarup Bhunia, and Rickard Ewetz, “E³-CODE: Embedded and Efficient Error-Correcting Code for Error-Resilient Neural Networks”, to appear in Design Automation Conference (DAC) (2026).
• [CVPR’26] Abdullah Al Nomaan Nafi, Habibur Rahaman, Zafaryab Haider, Tanzim Mahfuz, Fnu Suya, Swarup Bhunia, and Prabuddha Chakraborty, “DASH: A Meta-Attack Framework for Synthesizing Effective and Stealthy Adversarial Examples”, to appear in The IEEE/CVF Conference on Computer Vision and Pattern Recognition, (CVPR) (2026).
• [USENIX Security’26] Sanskar Amgain, Daniel Lobo, Atri Chatterjee, Swarup Bhunia, and Fnu Suya, “HAMLOCK: HArdware-Model LOgically Combined attack”, to appear in USENIX Security Symposium (USENIX Security) (2026).
• [DATE’26] Mahmudul Hasan, Sudipta Paria, Swarup Bhunia, and Tamzidul Hoque, “COVERT: Trojan Detection in COTS Hardware via Statistical Activation of Microarchitectural Events”, to appear in Design, Automation and Test in Europe Conference (DATE) (2026).
• [ISQED’26] Atri Chatterjee, Sudipta Paria, Aritra Dasgupta, Habibur Rahaman, Baibhab Chatterjee and Swarup Bhunia, “CRISP: Platform-Agnostic Unified Reconfigurable Hardware Security Primitive”, to appear in The 27^th International Symposium on Quality Electronic Design (ISQED) (2026).
• [AERA’26] Andrea Ramirez-Salgado, Lauren Eutsler, Anany Sharma, Woorin Hwang, Yessy E. Ambarwati, Talar Terzian, Megan Barnes, Nicole Dominguez, Dillon Donihue, Swarup Bhunia, Tamzidul Hoque, and Pasha Antonenko, “Engaging teenagers in community-centered edge AI projects,” to appear in the American Educational Research Association (AERA) (2026).
• [AERA’26] Lauren Eutsler, Megan Barnes, Andrea Ramirez-Salgado, Yessy E. Ambarwati, Woorin Hwang, Talar Terzian, Anany Sharma, Tamzidul Hoque, Swarup Bhunia, and Pasha Antonenko, “Listening to Teachers: Adapting a Microelectronics and AI Curriculum Through Participatory Design,” to appear in the American Educational Research Association (AERA) (2026).

2025

• [ICCD’25] Sudipta Paria, Aritra Dasgupta, Dinesh R. Ankireddy, Prabuddha Chakraborty, and Swarup Bhunia, “LLM-assisted Scalable Formal Verification”. IEEE International Conference on Computer Design (ICCD) (2025). [In Special Session, GenAI Meets Silicon: LLMs in Hardware Design, Verification, and Security].
• [NeurIPS Education’25] Andrea Ramirez-Salgado, Pasha Antonenko, Swarup Bhunia, Lauren Eutsler, Tamzidul Hoque, “Reimagining AI Education: Local, Tangible, and Personally Meaningful”. NeurIPS 2025 Education Program (NeurIPS Education) (2025).
• [SmartIoT’25] Ankan Ghosh, Sumaiya Afroz Mila, Zongwei Zhen, Cong Chen, Swarup Bhunia, Sandip Ray, “A Machine Learning Approach for Real-time Gait Analysis”. 9^th IEEE International Conference on Smart Internet of Things (SmartIoT) (2025). [Best Paper Runner-up Award].
• [ASEE ACE’25] Andrea Ramirez-Salgado, Pavlo Antonenko, Swarup Bhunia, Christine Wusylko, Woorin Hwang, Yessy Eka Ambarwati, “Voices of Hope: A Phenomenological Study on Women’s Self-Efficacy in Computer Engineering”. ASEE Annual Conference & Exposition (ASEE) (2025).
  [Abstract]
• [MLCAD’25] Dinesh R. Ankireddy, Sudipta Paria, Aritra Dasgupta, Sandip Ray, Swarup Bhunia, “LASSO: LLM-Aided Security Property Generation for Assertion-based SoC Verification”. ACM/IEEE International Symposium on Machine Learning for CAD (MLCAD): 1-10 (2025). [Best Paper Nomination].
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• [ICCAD’25] Raghul Saravanan, Sudipta Paria, Aritra Dasgupta, Swarup Bhunia, Sai Manoj Pudukotai Dinakarrao, “PROFUZZ: Directed Graybox Fuzzing via Module Selection and ATPG-Guided Seed Generation”. IEEE/ACM International Conference on Computer-Aided Design (ICCAD): 1-9 (2025).
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• [ITC’25] Sudipta Paria, Md Rezoan Ferdous, Aritra Dasgupta, Atri Chatterjee, Swarup Bhunia, “LITE: ATPG-Aware Lightweight Scan Instrumentation for Enhancing Test Efficiency”. International Test Conference (ITC): 339-348 (2025).
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• [MWSCAS’25] Junjun Huan, Jacob Pena, Zongwei Zhen, Swarup Bhunia, and Somyajit Manda, “A Wearable Ultrasound Device for Scapular Movement Tracking”. IEEE International Midwest Symposium on Circuits and Systems (MWSCAS) (2025).
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• [DAC’25] Tanzim Mahfuz, Sudipta Paria, Tasneem Farhana Suha, Swarup Bhunia, and Prabuddha Chakraborty, “POLARIS: Explainable Artificial Intelligence for Mitigating Power Side-Channel Leakage”. Design Automation Conference (DAC): 1-7 (2025).
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• [VTS’25] Dinesh Reddy Ankireddy, Sudipta Paria, Aritra Dasgupta, Sandip Ray, and Swarup Bhunia, “CLIP: A Structural Approach to Cut Points Matching for Logic Equivalence Checking”. IEEE VLSI Test Symposium (VTS): 1-7 (2025).
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• [VTS’25] Tanzim Mahfuz, Pravin Gaikwad, Swarup Bhunia, and Prabuddha Chakraborty, “SALTY: Explainable Artificial Intelligence Guided Structural Analysis for Hardware Trojan Detection”. IEEE VLSI Test Symposium (VTS): 1-7 (2025).
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• [VTS’25] Sudipta Paria, Aritra Dasgupta, and Swarup Bhunia, “Towards Automated Verification of IP and COTS: Leveraging LLMs in Pre- and Post-Silicon Stages”. IEEE VLSI Test Symposium (VTS): 1-5 (2025). [LLM Applications in VLSI Testing and Security]
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• [AERA’25] Andrea Ramirez-Salgado, Pasha Antonenko, Maya Israel, Kara M. Dawson, and Swarup Bhunia, “Advancing Transcendental Phenomenology as a Methodology for Exploring the Needs and Voices of Underrepresented Groups”. American Educational Research Association (AERA) (2025).

2024

• [HOST’24] Sudipta Paria, Aritra Dasgupta, and Swarup Bhunia, “DiSPEL: A Framework for SoC Security Policy Synthesis and Distributed Enforcement”. IEEE International Workshop on Hardware-Oriented Security and Trust (HOST): 271-281 (2024).
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• [ATS’24] Habibur Rahaman, Atri Chatterjee, and Swarup Bhunia, “SAMURAI: A Framework for Safeguarding Against Malicious Usage and Resilience of AI”. Asian Test Symposium (ATS): 1-6 (2024).
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• [ATS’24] Sudipta Paria, Aritra Dasgupta, and Swarup Bhunia.”LATENT: Leveraging Automated Test Pattern Generation for Hardware Trojan Detection”. Asian Test Symposium (ATS): 1-6 (2024). [Best Paper Nomination].
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• [ATS’24] Habibur Rahaman and Swarup Bhuinia, “Secure AI Systems: Emerging Threats and Defense Mechanisms”. Asian Test Symposium (ATS): 1-6 (2024).
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• [PAINE’24] Moshiur Rahaman, Rasheed Almawzan, Aritra Dasgupta, Sudipta Paria and Swarup Bhuinia, “United We Protect: Protecting IP Confidentiality with Integrated Transformation and Redaction”. IEEE Physical Assurance and Inspection of Electronics (PAINE): (2024).
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• [ISVLSI’24] Reiner N. Dizon-Paradis, Aritra Dasgupta, Rohan Reddy Kalavakonda, Swarup Bhunia: “Pasteables: A Flexible and Smart “Stick-and-Peel” Wearable Platform for Fitness and Athletics”. IEEE Computer Society Annual Symposium on VLSI (ISVLSI): (2024).
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• [ISVLSI’24] Rasheed Almawzan, Sudipta Paria, Aritra Dasgupta, Kostas Amberiadis, Swarup Bhunia: “IP Security in Structured ASIC: Challenges and Prospects”. IEEE Computer Society Annual Symposium on VLSI (ISVLSI): 397-402 (2024).
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• [ISVLSI’24] Aritra Dasgupta, Sudipta Paria, Prabuddha Chakraborty, Swarup Bhunia: “Splitting the Secrets: A Cooperative Trust Model for System-on-Chip Designs with Untrusted IPs”. IEEE Computer Society Annual Symposium on VLSI (ISVLSI): 325-330 (2024).
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• [ISVLSI’24] Prabuddha Chakraborty, Swarup Bhunia: “An Intelligent Memory Framework for Resource Constrained IoT Systems”.  IEEE Computer Society Annual Symposium on VLSI (ISVLSI): 296-299 (2024).
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• [GLSVLSI’24] Rasheed Almawzan, Atri Chatterjee, Aritra Dasgupta, Swarup Bhunia: “LISA: A Multi-Layered Iterative Framework for Hardening Obfuscation with Modular Unit Transformations”. ACM Great Lakes Symposium on VLSI (GLSVLSI): 588-591 (2024).
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• [GLSVLSI’24] Sudipta Paria, Aritra Dasgupta, Swarup Bhunia: “Navigating SoC Security Landscape on LLM-Guided Paths”. ACM Great Lakes Symposium on VLSI (GLSVLSI): 252-257 (2024).
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• [BIOCAS’24] Deepanshu Trivedi, Junjun Huan, Arjuna Madanayake, Swarup Bhunia, Soumyajit Mandal: “Compressed Plane-Wave Compounding for Efficient Imaging on Portable Ultrasound Devices”. IEEE Biomedical Circuits and Systems Conference (BioCAS): 1-5 (2024).
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2023

• [SOCC’23] Prabuddha Chakraborty, Tasneem Suha, Swarup Bhunia, “Hardware Specification Aware Timing Side Channel Security Analysis”. ACM Symposium on Cloud Computing (SOCC): 1-6 (2023).
  [Abstract | PDF]
• [IJCNN’23] Krishnendu Guha, Amit Ranjan Trivedi, Swarup Bhunia, “Energy Efficient Memory-based Inference of LSTM by Exploiting FPGA Overlay”. International Joint Conference on Neural Networks (IJCNN): 1-7 (2023).
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2022

• [AICAS’22] Ahish Shylendra, Priyesh Shukla, Swarup Bhunia, Amit Ranjan Trivedi: “Analog-Domain Time-Series Moment Extraction for Low Power Predictive Maintenance Analytics”. IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS): 9-12 (2022).
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• [ASIANHOST’22] Jonathan Cruz, Pravin Gaikwad, Swarup Bhunia, “Analysis of Hardware Trojan Resilience Enabled through Logic Locking”. Asian Hardware Oriented Security and Trust Symposium (AsianHOST): 1-6 (2022).
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• [ASIANHOST’22] Jonathan Cruz, Pravin Gaikwad, Abhishek Nair, Prabuddha Chakraborty, Swarup Bhunia: “A Machine Learning Based Automatic Hardware Trojan Attack Space Exploration and Benchmarking Framework”. Asian Hardware Oriented Security and Trust Symposium (AsianHOST): 1-6 (2022).
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• [ASPDAC’22] Lakshmy, Chester Rebeiro, Swarup Bhunia: “FORTIFY: Analytical Pre-Silicon Side-Channel Characterization of Digital Designs”. Asia and South Pacific Design Automation Conference (ASP-DAC): 660-665 (2022).
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• [DAC’22] Aritra Bhattacharyay, Prabuddha Chakraborty, Jonathan Cruz, Swarup Bhunia: “VIPR-PCB: a machine learning based golden-free PCB assurance framework”. Design Automation Conference (DAC): 793-798 (2022).
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• [ICCAD’22] Swarup Bhunia, Amitabh Das, Saverio Fazzari, Vivian Kammler, David Kehlet, Jeyavijayan Rajendran, Ankur Srivastava: “Hardware IP Protection against Confidentiality Attacks and Evolving Role of CAD Tool”. IEEE/ACM International Conference on Computer-Aided Design (ICCAD): 25:1-25:8 (2022).
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• [ITC’22] Prabuddha Chakraborty, Swarup Bhunia: “AI-Driven Assurance of Hardware IP against Reverse Engineering Attacks”. International Test Conference (ITC): 627-636 (2022).
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• [SMARTIOT’22] Reiner N. Dizon-Paradis, Oliver Ferrigno, Ishamor Reid, Swarup Bhunia: “Light Pollution Monitoring Using A Modular IoT Sensor Platform”. IEEE International Conference on Smart Internet of Things (SmartIoT): 28-35 (2022).
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• [VLSID’22] Abdulrahman Alaql, Aritra Dasgupta, Md Moshiur Rahman, Swarup Bhunia: “SEVA: Structural Analysis based Security Evaluation of Sequential Locking”. International Conference on VLSI Design (VLSID): 126-131 (2022).
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2021

• [AsianHOST’21] Kshitij Raj, Arrush Hegde, Atul Prasad Deb Nath, Swarup Bhunia, Sandip Ray: “SSEL: An Extensible Specification Language for SoC Security”. Asian Hardware Oriented Security and Trust Symposium (AsianHOST): 1-6 (2021).
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• [DATE’21] Sandip Ray, Atul Prasad Deb Nath, Kshitij Raj, Swarup Bhunia: “CASTLE: Architecting Assured System-on-Chip Firmware Integrity”. Design, Automation and Test in Europe Conference (DATE): 1781-1786 (2021).
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• [GLSVLSI’21] Sandip Ray, Atul Prasad Deb Nath, Kshitij Raj, Swarup Bhunia: “The Curious Case of Trusted IC Provisioning in Untrusted Testing Facilities”. ACM Great Lakes Symposium on VLSI (GLSVLSI): 207-212 (2021).
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• [ISQED’21] Shuo Yang, Prabuddha Chakraborty, Patanjali SLPSK, Swarup Bhunia: “Trusted Electronic Systems with Untrusted COTS”. International Symposium on Quality Electronic Design (ISQED) :198-203 (2021).
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• [ISQED’21] Abdulrahman Alaql, Xinmu Wang, Md Moshiur Rahman, Swarup Bhunia: “SOMA: Security Evaluation of Obfuscation Methods via Attack Sequencing”. International Symposium on Quality Electronic Design (ISQED): 381-386 (2021).
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• [MWSCAS’21] Naren Vikram Raj Masna, Rohan Reddy Kalavakonda, Reiner Dizon, Swarup Bhunia: “Smart and Connected Mask for Protection beyond the Pandemic”. IEEE International Midwest Symposium on Circuits and Systems (MWSCAS): 676-679 (2021).
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2020

• [VTC’20] Prabuddha Chakraborty, Robert C Parker, Jonathan Cruz, Tamzidul Hoque, and Swarup Bhunia, “P2C2: Peer-to-Peer Car Charging”. IEEE Vehicular Technology Conference (VTC): 1-5 (2020).
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• [DATE’20] Milind Srivastava, Patanjali SLPSK, Indrani Roy, Chester Rebeiro, Aritra Hazra, Swarup Bhunia, “SOLOMON: An Automated Framework for Detecting Fault Attack Vulnerabilities in Hardware”. Design, Automation and Test in Europe Conference (DATE): 310-313 (2020).
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• [GLSVLSI’20] Tamzidul Hoque, Patanjali SLPSK, Swarup Bhunia, “Trust Issues in COTS: The Challenges and Emerging Solution”. ACM Great Lakes Symposium on VLSI (GLSVLSI): 211-216 (2020).
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• [ISQED’20] Ahish Shylendra, Priyesh Shukla, Swarup Bhunia, and Amit Ranjan Trivedi, “Fault Attack Detection in AES by Monitoring Power Side-Channel Statistics”. International Symposium on Quality Electronic Design (ISQED) 219-224 (2020).
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2019

• [ASIANHOST’19] Abdulrahman Alaql, Domenic Forte, and Swarup Bhunia, “Sweep to the Secret: A Constant Propagation Attack on Logic Locking”. Asian Hardware Oriented Security and Trust Symposium (AsianHOST) 1-6 (2019).
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• [ICCAD’19] Jungmin Park, JP Park, Swarup Bhunia, Alex Cho, and Mark Tehranipoor, “SCR-QRNG: Side-Channel Resistant Design using Quantum Random Number Generator”. IEEE/ACM International Conference on Computer-Aided Design (ICCAD) 1-8 (2019).
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• [NAECON’19] Nicholas Olexa, Swarup Bhunia, Soumyajit Mandal, and Rashmi Jha, “ReRAM-Based Intrinsically Secure Memory: A Feasibility Analysis”. National Aerospcae and Electronics Conference (NAECON): 218-225 (2019).
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• [HOST’19] Prabuddha Chakraborty, Jonathan Cruz, and Swarup Bhunia, “SURF: Joint Structural Functional Attack on Logic Locking”. IEEE International Workshop on Hardware-Oriented Security and Trust (HOST): 181-190 (2019).
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• [VTS’19] Abdulrahman Alaql, Tamzidul Hoque, Domenic Forte, Swarup Bhunia, “Quality Obfuscation for Error-Tolerant and Adaptive Hardware IP Protection”. IEEE VLSI Test Symposium (VTS): 1-6 (2019).
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2018

• [ASIANHOST’18] Prabuddha Chakraborty, Jonathan Cruz, and Swarup Bhunia, “SAIL: Machine Learning Guided Structural Analysis Attack on Hardware Obfuscation”. Asian Hardware Oriented Security and Trust Symposium (AsianHOST): 56-61 (2018).
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• [ITC’18] Tamzidul Hoque, Jonathan Cruz, Prabuddha Chakraborty, and Swarup Bhunia, “Hardware IP Trust Validation: Learn (the Untrustworthy) and Verify”. International Test Conference (ITC): 1-10 (2018)
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• [ISTFA’18] Haoting Shen, M Tanjidur Rahman, Navid Asadizanjan, Mark Tehranipoor, and Swarup Bhunia, “Coating-Based PCB Protection against Tampering, Snooping, EM Attack, and X-ray Reverse Engineering”.  44th International Symposium for Testing and Failure Analysis (ISTFA): 290-294 (2018).
  [Abstract]
• [ISLPED’18] Ahish Shylendra, Swarup Bhunia, and Amit Ranjan Trivedi, “Intrinsic and Database-free Watermarking in ICs by Exploiting Process and Design Dependent Variability in Metal-Oxide-Metal Capacitances”. IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED): 44:1-44:6 (2018).
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• [ISVLSI’18] Atul Prasad Debnath, Swarup Bhunia, and Sandip Ray, “ArtiFact: Architecture and CAD Flow for Efficient Formal Verification of SoC Security Policies”. IEEE Computer Society Annual Symposium on VLSI (ISVLSI): 411-416 (2018).
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• [ISVLSI’18] Kai Yang, Jungmin Park, Mark Tehranipoor, and Swarup Bhunia, “Robust Timing Attack Countermeasure on Virtual Hardware”. IEEE Computer Society Annual Symposium on VLSI (ISVLSI): 148-153 (2018).
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• [HILTON-HEAD’18] Mehrdad Ramezani, Angela Newsome, Mayur Ghatge, Fengchao Zhang, Swarup Bhunia, and Roozbeh Tabrizian, “A Nanomechanical Identification Tag Technology for Traceability and Authentication Applications”. Hilton Head 2018 Solid-State Sensors, Actuators & Microsystems Workshop (HILTON-HEAD): 206-209 (2018).
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• [HOST’18] Kai Yang, Jungmin Park, Mark Tehranipoor, and Swarup Bhunia, “Hardware virtualization for protection against power analysis attack”. IEEE International Workshop on Hardware-Oriented Security and Trust (HOST): 167-172 (2018).
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• [VTS’18] Tamzidul Hoque, Xinmu Wang, Abhishek Basak, Robert Karam, and Swarup Bhunia, “Hardware Trojan Attack in Embedded Memory”. IEEE VLSI Test Symposium (VTS): 1-6 (2018).
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• [NEMS’18] Angela Newsome, Mehrdad Ramezani, Mayur Ghatge, Fengchao Zhang, Swarup Bhunia, and Roozbeh Tabrizian, “Multi-Mode Micromechanical Resonant Tags for Traceability and Authentication Applications”. IEEE International Conference on Nano/Micro Engineered and Molecular Systems (NEMS): 275-279 (2018).
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• [DATE’18] Jonathan Cruz, Yuanwen Huang, Prabhat Mishra, and Swarup Bhunia, “An automated configurable Trojan insertion framework for dynamic trust benchmarks”. Design, Automation and Test in Europe Conference (DATE) 1598-1603 (2018).
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• [ASPDAC’18] Sandip Ray, Atul Prasad Deb Nath, Abhishek Basak, and Swarup Bhunia, “System-on-chip security architecture and CAD framework for hardware patch”. Asia and South Pacific Design Automation Conference (ASP-DAC): 733-738 (2018).
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2017

• [BIOCAS’17] Fengchao Zhang, Naren Masna, Cheng Chen, Soumyajit Mandal, and Swarup Bhunia, “Authentication and traceability of food products through the supply chain using NQR spectroscopy”. IEEE Biomedical Circuits and Systems Conference (BioCAS): 1-4 (2017).
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• [ASIANHOST’17] Robert Karam, Tamzidul Hoque, Kevin Butler, and Swarup Bhunia, “Mixed-granular architectural diversity for device security in the Internet of Things”. Asian Hardware Oriented Security and Trust Symposium (AsianHOST): 73-78 (2017).
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• [MWSCAS’17] Jungmin Park, Massimiliano Corba, Antonio E. de la Serna, Richard L. Vigeant, Mark Tehranipoor, and Swarup Bhunia, “ATAVE: A framework for automatic timing attack vulnerability evaluation”. IEEE International Midwest Symposium on Circuits and Systems (MWSCAS): 559-562 (2017).
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• [MWSCAS’17] Kai Yang, Robert Karam, and Swarup Bhunia, “Interleaved logic-in-memory architecture for energy-efficient fine-grained data processing”. IEEE International Midwest Symposium on Circuits and Systems (MWSCAS): 409-412 (2017).
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• [MWSCAS’17] Tonmoy Dhar, Swarup Bhunia, and Amit Trivedi, “A solitary protection measure against scan chain, fault injection, and power analysis attacks on AES”. IEEE International Midwest Symposium on Circuits and Systems (MWSCAS): 575-578 (2017).
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• [ASPDAC’17] Gustavo K. Contreras, Adib Nahiyan, Swarup Bhunia, Domenic Forte, Mark Tehranipoor, “Security vulnerability analysis of design-for-test exploits for asset protection in SoCs”. Asia and South Pacific Design Automation Conference (ASP-DAC): 617-622 (2017).
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• [ASPDAC’17] Robert Karam, Tamzidul Hoque, Sandip Ray, Mark Tehranipoor, and Swarup Bhunia, “MUTARCH: Architectural diversity for FPGA device and IP security”. Asia and South Pacific Design Automation Conference (ASP-DAC): 611-616 (2017).
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2016

• [CCS’16] Yuanwen Huang, Swarup Bhunia, and Prabhat Mishra, “MERS: Statistical Test Generation for Side-Channel Analysis based Trojan Detection”. ACM Conference on Computer and Communications Security (CCS): 130-141 (2016).
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• [RECONFIG’16] Robert Karam, Tamzidul Hoque, Sandip Ray, Mark Tehranipoor and Swarup Bhunia, “Robust bitstream protection in FPGA-based systems through low-overhead obfuscation”. International Conference on Reconfigurable Computing and FPGAS (ReConFig): 1-8 (2016).
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• [BIOCAS’16] Robert Karam, Steve Majerus, Dennis Bourbeau, Margot Damaser, and Swarup Bhunia, “Ultralow-power data compression for implantable bladder pressure monitor: Algorithm and hardware implementation”. IEEE Biomedical Circuits and Systems Conference (BioCAS): 500-503 (2016).
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• [HI-POCT’16] Sumaiya Shomaji, Abhishek Basak, Soumyajit Mandal, Swarup Bhunia, “A Wearable Carotid Ultrasound Assembly for Early Detection of Cardiovascular Diseases”. IEEE Healthcare Innovation Point-of- Care Technologies (HI-POCT): 17-20 (2016).
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• [ISTFA’16] Zimu Guo, Bicky Shakya, Haoting Shen, Swarup Bhunia, Navid Asadizanjani, Domenic Forte, Mark Tehranipoor, “A New Methodology to Protect PCBs from Non-destructive Reverse Engineering”. International Symposium for Testing and Failure Analysis (ISTFA): 347-356 (2016).
  [Abstract]
• [ICCAD’16] Dylan Ismari, Charles Lamech, Swarup Bhunia, Fareena Saqib, and James Plusquellic, “On detecting delay anomalies introduced by hardware trojans”. IEEE/ACM International Conference on Computer-Aided Design (ICCAD): 1-7 (2016).
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• [EMBC’16] Robert Karam, Swarup Bhunia, Steve Majerus, Steven Brose, Margot S. Damaser, Dennis Bourbeau, “Real-time, autonomous bladder event classification and closed-loop control from single-channel pressure data”. Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC): 5789-5792 (2016).
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• [DAC’16] Abhishek Basak, Swarup Bhunia, and Sandip Ray, “Exploiting design-for-debug for flexible SoC security architecture”. Design Automation Conference (DAC): 167:1-167:6 (2016).
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• [ISQED’16] Steven Paley, Tamzidul Hoque, and Swarup Bhunia, “Active protection against PCB physical tampering”. International Symposium on Quality Electronic Design (ISQED): 356-361 (2016).
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• [DATE’16] Fengchao Zhang, James Plusquellic, and Swarup Bhunia, “Current based PUF exploiting random variations in SRAM cells”. Design, Automation and Test in Europe Conference (DATE): 277-280 (2016).
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• [ASPDAC’16] Andrew Hennessy, Yu Zheng, and Swarup Bhunia, “JTAG-based robust PCB authentication for protection against counterfeiting attacks”. Asia and South Pacific Design Automation Conference (ASP-DAC): 56-61  (2016).
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2015

• [ITC’15] Abhishek Basak, Fengchao Zhang, and Swarup Bhunia, “PiRA: IC authentication utilizing intrinsic variations in pin resistance”. International Test Conference (ITC): 1-8 (2015).
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• [ICCAD’15] Abhishek Basak, Sandip Ray, and Swarup Bhunia, “A Flexible Architecture for Systematic Implementation of SoC Security Policies”. IEEE/ACM International Conference on Computer-Aided Design (ICCAD): 536-543 (2015).
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• [DAC’15] Jae-Won Jang, Jongsun Park, Swaroop Ghosh, and Swarup Bhunia, “Self-correcting STTRAM under magnetic field attacks”. Design Automation Conference (DAC): 77:1-77:6 (2015).
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• [VTS’15] Andrew Hennessy, Fengchao Zhang, and Swarup Bhunia, “Robust counterfeit PCB detection exploiting intrinsic trace impedance variations”. 33rd IEEE VLSI Test Symposium (VTS): 1-6 (2015).
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2014

• [DAC’14] Yu Zheng, Abhishek Basak, and Swarup Bhunia, “CACI: Dynamic Current Analysis Towards Robust Recycled Chip Identification”. Design Automation Conference (DAC): 88:1-88:6 (2014).
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• [ICCAD’14] Wenjie Che, Swarup Bhunia and Jim Plusquellic, “A non-volatile memory based physically unclonable function without helper data”. IEEE/ACM International Conference on Computer-Aided Design (ICCAD): 148-153 (2014).
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• [VTS’14] Abhishek Basak, Yu Zheng, and Swarup Bhunia, “Active defense against counterfeiting attacks through robust antifuse-based on-chip locks”. IEEE VLSI Test Symposium (VTS): 1-6 (2014).
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• [GLSVLSI’14] Wenchao Qian, Robert Karam, and Swarup Bhunia, “Trade-off between energy and quality of service through dynamic operand truncation and fusion”. ACM Great Lakes Symposium on VLSI (GLSVLSI): 79-80 (2014).
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• [GLSVLSI’14] Sanchita Mal-Sarkar, Aswin Krishna, Anandaroop Ghosh and Swarup Bhunia, “Hardware trojan attacks in FPGA devices: threat analysis and effective counter measures”. ACM Great Lakes Symposium on VLSI (GLSVLSI): 287-292 (2014).
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• [NEMS’14] Vaishnavi Ranganathan, Srihari Rajgopal, Mehran Mehregany, and Swarup Bhunia, “Analysis of practical scaling limits in nanoelectromechanical switches”. IEEE International Conference on Nano/Micro Engineered and Molecular Systems (NEMS): 471-476 (2014).
  [Abstract | PDF]

2013

• [IEDM’13] Tina He, Vaishnavi Ranganathan, Rui Yang, Srihari Rajgopal, Mary Anne Tupta, Mehran Mehregany, Swarup Bhunia, and Philip X.-L. Feng, “Silicon Carbide (SiC) Nanoelectromechanical Switches and Logic Gates with Long Cycles and Robust Performance in Ambient Air and at High Temperature”. IEEE International Electron Devices Meeting (IEDM) (2013).
  [Abstract | PDF]
• [NANOARCH’13] Hadi Hajimiri, Prabhat Mishra, Swarup Bhunia, Branden Long, Yibo Li, and Rashmi Jha, “Content-aware encoding for improving energy efficiency in multi-level cell resistive random access memory”. IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH): 76-81 (2013).
  [Abstract | PDF]
• [NANOARCH’13] Vaishnavi Ranganathan, Tina He, Srihari Rajgopal, Mehran Mehregany, Philip X.-L. Feng, and Swarup Bhunia, “Robust Nanomechanical Non-Volatile Memory for Computing at Extreme”.  9th IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) (2013).
  [Abstract | PDF]
• [DAC’13] Yu Zheng, MaryamSadat Hashemian, and Swarup Bhunia, “RESP: a robust physical unclonable function retrofitted into embedded SRAM array”. Design Automation Conference (DAC): 60:1-60:9 (2013).
  [Abstract | PDF]
• [DAC’13] Xinmu Wang, Wen Yueh, Debapriya Basu Roy, Yu Zheng, Seetharam Narasimhan, Saibal Mukhopadhyay, Debdeep Mukhopadhyay, and Swarup Bhunia, “Role of power grid in side channel attack and power-grid-aware secure design. Design Automation Conference (DAC) : 78:1-78:9 (2013).
  [Abstract | PDF]
• [TRANSDUCERS’13] Tina He, Vaishnavi Ranganathan, Rui Yang, Srihari Rajgopal, Swarup Bhunia, Mehran Mehregany, and Philip X.-L. Feng, “Time-Domain AC Measurement of SiC Nanoelectromechanical Switches toward High Speed Operations”. International Conference on Solid-State Sensors, Actuators and Microsystems (Transducers) (2013).
  [Abstract | PDF]
• [MRS’13] Yibo Li, Wenbo Chen, Ammaarah El-Amin, Rashmi Jha, Swarup Bhunia, and Philip X.-L. Feng, “A Reconfigurable Sensing and Computing Platform for Artificial Electronic Skins”, MRS Spring Meeting (Symposium TT: Materials and Processes for Artificial Skin), (MRS) (2013).
• [NEMS’13] Tina He, Rui Yang, Srihari Rajgopal, Swarup Bhunia, Mehran Mehregany, and Philip X.-L. Feng, “Dual-gate silicon carbide (SiC) lateral nanoelectromechanical switches”. IEEE International Conference on Nano/Micro Engineered and Molecular Systems (NEMS): 554-557 (2013). [Best Student Paper Award].
  [Abstract | PDF]
• [ASPDAC’13] Yu Zheng, Aswin Raghav Krishna, and Swarup Bhunia, “ScanPUF: Robust ultralow-overhead PUF using scan chain”. Asia and South Pacific Design Automation Conference (ASP-DAC): 626-631 (2013).
  [Abstract | PDF]
• [MEMS’13] Tina He, Rui Yang, Srihari Rajgopal, Mary Anne Tupta, Swarup Bhunia, Mehran Mehregany, and Philip X.-L. Feng, “Robust Silicon Carbide (SiC) Nanoelectromechanical Switches with Long Cycles in Ambient and High Temperature Conditions”. IEEE International Conference on Micro Electro Mechanical Systems (MEMS): 516-519 (2013).
  [Abstract | PDF]
• [PHT’13] Abhishek Basak, Vaishnavi Ranganathan, and Swarup Bhunia, “A Wearable Ultrasonic Assembly for Point-Of-Care Autonomous Diagnostics of Malignant Growth”. IEEE EMBS Special Topic Conference on Point-of-Care Healthcare Technologies (PHT): 128-131 (2013). [Student Paper Competition Winner (2^nd Place)].
  [Abstract | PDF]
• [VLSID’13] Maryamsadat Hashemian and Swarup Bhunia, “Ultra-Power and Robust Embedded Memory for Bioimplantable Microsystems”. International Conference on VLSI Design (VLSID): 66-71 (2013).
  [Abstract | PDF]
• [VLSID’13] Hadi Hajimiri, Prabhat Mishra, and Swarup Bhunia, “Dynamic Cache Tuning for Efficient Memory Based Computing in Multicore Architectures”. International Conference on VLSI Design (VLSID): 49-54 (2013).
  [Abstract | PDF]

2012

• [DFTS’12] Xinmu Wang, Seetharam Narasimhan, Aswin Krishna, Tatini Mal-Sarkar, and Swarup Bhunia, “Software exploitable hardware Trojans in embedded processor”. IEEE International Symposium on Defect Tolerance in VLSI and Nanotechnology Systems (DFT): 55-58 (2012). [Student Paper Award].
  [Abstract | PDF]
• [EMBC’12] Abhishek Basak, Vaishnavi Ranganathan, Seetharam Narasimhan, and Swarup Bhunia, “Implantable ultrasonic dual functional assembly for detection and treatment of anomalous growth”.  Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC): 170-173 (2012). [Student Best Paper Finalist].
• [Abstract | PDF]
• [GLSVLSI’12] Kamran Rahmani, Prabhat Mishra, and Swarup Bhunia, “Memory-based Computing for Performance and Energy Improvement in Multicore Architectures”. 22nd ACM Great Lakes Symposium on VLSI Conference (GLSVLSI): 287-290 (2012).
  [Abstract | PDF]
• [VLSID’12] Xinmu Wang, Seetharam Narasimhan, and Swarup Bhunia, “SCARE: Side-Channel Analysis Based Reverse Engineering for Post-Silicon Validation”. International Conference on VLSI Design (VLSID): 304-309 (2012).
  [Abstract | PDF]
• [VLSID’12] Anandaroop Ghosh, Somnath Paul, and Swarup Bhunia, “Energy-Efficient Application Mapping in FPGA through Computation in Embedded Memory Blocks”. International Conference on VLSI Design (VLSID): 424-429 (2012).
  [Abstract | PDF]
• [VLSID’12] Lei Wang, Somnath Paul, and Swarup Bhunia, “Width-Aware Fine-Grained Dynamic Supply Gating: A Design Methodology for Low-Power Datapath and Memory”. International Conference on VLSI Design (VLSID): 340-345 (2012). [Best paper award]
  [Abstract | PDF]

2011

• [InfoSecHiComNet’11] Rajat Subhra Chakraborty, Seetharam Narasimhan and Swarup Bhunia, “Embedded Software Security through Key-Based Control Flow Obfuscation”. International Conference on Security Aspects in Information Technology (InfoSecHiComNet): 30-44 (2011).
  [Abstract | PDF]
• [EMBC’11] Abhishek Basak, Seetharam Narasimhan, and Swarup Bhunia, “Low Power Implantable Ultrasound Imager for Online Monitoring of Tumor Growth”. 33rd Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC): 2858-2861 (2011).
  [Abstract | PDF]
• [CHES’11] Aswin Raghav Krishna, Seetharam Narasimhan, Xinmu Wang, and Swarup Bhunia, “MECCA: A Robust Low-Overhead PUF Using Embedded Memory Array”. Cryptographic Hardware and Embedded Systems (CHES): 407-420 (2011). [Best paper candidate]
  [Abstract | PDF]
  
• [NANOARCH’11] Xinmu Wang, Seetharam Narasimhan, Somnath Paul, and Swarup Bhunia, “NEMTronics: Symbiotic integration of nanoelectronic and nanomechanical devices for energy-efficient adaptive computing”. IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH): 210-217 (2011).
  [Abstract | PDF]
• [HOST’11] Seetharam Narasimhan, Xinmu Wang, Dongdong Du, Rajat Subhra Chakraborty, and Swarup Bhunia, “TeSR: A robust Temporal Self-Referencing approach for Hardware Trojan detection”. IEEE International Workshop on Hardware-Oriented Security and Trust (HOST): 71-74 (2011).
  [Abstract | PDF]
• [HEALTHCOM’11] Abhishek Basak, Seetharam Narasimhan, and Swarup Bhunia, “KiMS: Kids’ Health Monitoring System at Day-Care Centers using Wearable Sensors and Vocabulary-based Acoustic Signal Processing”. 13th IEEE International Conference on e-Health Networking, Application & Services (Healthcom): 1-8 (2011).
  [Abstract | PDF]
• [NVMW’11] Subho Chatterjee, Saibal Mukhopadhyay, Mitchelle Rasquinha, Sudhakar Yalamanchili, Swarup Bhunia, and Somnath Paul, “Energy Efficient Circuit-System Codesign For Spin Torque Transfer Random Access Memory (STTRAM) In Submicron Technologies”. Non-Volatile Memories Workshop (NVMW) (2011).
• [DATE’11] Xinmu Wang, Seetharam Narasimhan, Aswin Krishna, Francis G. Wolff, Hari and Swarup Bhunia, “High-temperature (>500°C) reconfigurable computing using silicon carbide NEMS switches”. Design, Automation and Test in Europe Conference (DATE): 1065-1070 (2011).
  [Abstract | PDF]
• [DATE’11] Subidh Ali, Debdeep Mukhopadhyay, Rajat Subhra Chakraborty, and Swarup Bhunia, “Multi-level attacks: An emerging security concern for cryptographic hardware”. Design, Automation and Test in Europe Conference (DATE): 1176-1179 (2011).
  [Abstract | PDF]
• [VLSID’11] Keerthi Kunaparaju, Seetharam Narasimhan, and Swarup Bhunia, “VaROT: Methodology for Variation-Tolerant DSP Hardware Design Using Post-Silicon Truncation of Operand Width”. International Conference on VLSI Design (VLSID): 310-315 (2011).
  [Abstract | PDF]

2010

• [AHS’10] Seetharam Narasimhan, Somnath Paul, Rajat Subhra Chakraborty, Francis Wolff, Christos Papachristou, Daniel Weyer, and Swarup Bhunia, “System level self-healing for parametric yield and reliability improvement under power bound”. NASA/ESA Conference on Adaptive Hardware and Systems (AHS): 52-58 (2010).
  [Abstract | PDF]
  
• [CHES’10] Rajat Subhra Chakraborty and Swarup Bhunia, “Embedded Software Security through Key-Based Control Flow Obfuscation”. Cryptographic Hardware and Embedded Systems (CHES): 30-44 (2010).
  [Abstract | PDF]
• [EMBC’10] Seetharam Narasimhan, Xinmu Wang, and Swarup Bhunia, “Implantable Electronics: Emerging Design Issues and An Ultra Light-weight Security Solution”. Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC): 6425-6428 (2010).
  [Abstract | PDF]
• [IGCC’10] Seetharam Narasimhan, David McIntyre, Yu Zhou, Francis Wolff, Daniel Weyer, and Swarup Bhunia, “A supply-demand model based scalable energy management system for improved energy utilization efficiency”. International Conference on Green Computing (ICGC): 97-105 (2010).
  [Abstract | PDF]
• [CHES’10] Dongdong Du, Seetharam Narasimhan, Rajat Subhra Chakraborty and Swarup Bhunia, “Self-referencing: A Scalable Side-Channel Approach for Hardware Trojan Detection”. Cryptographic Hardware and Embedded Systems (CHES): 173-187 (2010)
  [Abstract | PDF]
• [ISLPED’10] Somnath Paul and Swarup Bhunia, “VAIL: variation-aware issue logic and performance binning for processor yield and profit improvement”. IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED): 37-42 (2010).
  [Abstract | PDF]
• [IOLTS’10] David McIntyre, Francis Wolff, Chris Papachristou, and Swarup Bhunia, “Trustworthy computing in a multi-core system using distributed scheduling”. IEEE Symposium on On-Line Testing (IOLTS): 211-213 (2010).
  [Abstract | PDF]
• [NAECON’10] Chris Papachristou, Swarup Bhunia, and Francis Wolff, “Network Calibration of Embedded Sensors”. IEEE National Aerospace and Electronics Conference (NAECON): 269-274 (2010).
  [Abstract | PDF]
• [HOST’10] Dongdong Du, Seetharam Narasimhan, Rajat Subhra Chakraborty, Chris Papachristou, Somnath Paul, and Swarup Bhunia, “Multiple-Parameter Side-Channel Analysis: A Non-invasive Hardware Trojan Detection Approach”. IEEE International Workshop on Hardware-Oriented Security and Trust (HOST): 13-18 (2010). [Best paper candidate].
  [Abstract | PDF]
• [VLSID’10] Rajat Subhra Chakraborty and Swarup Bhunia, “RTL Hardware IP Protection Using Key-Based Control and Data Flow Obfuscation”. International Conference on VLSI Design (VLSID): 405-410 (2010).
  [Abstract | PDF]

2009

• [NANO’09] Somnath Paul, Subho Chatterjee, Saibal Mukhopadhyay and Swarup Bhunia, “Nanoscale Reconfigurable Computing Using Non-Volatile 2-D STTRAM Array”. 9^th International Conference on Nanotechnology (NANO): 880-883 (2009).
  [Abstract | PDF]
• [ICCAD’09] Somnath Paul, Subho Chatterjee, Saibal Mukhopadhyay and Swarup Bhunia, “A circuit-software co-design approach for improving EDP in reconfigurable frameworks”. IEEE International Conference on Computer-Aided Design (ICCAD): 109-112 (2009).
  [Abstract | PDF]
  
• [ICCAD’09] Somnath Paul, Saibal Mukhopadhyay and Swarup Bhunia, “A variation-aware preferential design approach for memory based reconfigurable computing”. IEEE International Conference on Computer-Aided Design (ICCAD): 180-183 (2009).
  [Abstract | PDF]
• [ICCAD’09] Rajat Subhra Chakraborty and Swarup Bhunia, “Security against hardware Trojan through a novel application of design obfuscation”. IEEE International Conference on Computer-Aided Design (ICCAD): 113-116 (2009).
  [Abstract | PDF]
• [HOST’09] Rajat Subhra Chakraborty and Swarup Bhunia, “Security Through Obscurity: An Approach for Protecting Register Transfer Level Hardware IP”. IEEE International Workshop on Hardware-Oriented Security and Trust (HOST): 96-99 (2009).
  [Abstract | PDF]
• [HOST’09] David McIntyre, Francis Wolff, Chris Papachristou, Swarup Bhunia and Dan Weyer, “Dynamic Evaluation of Hardware Trust”. IEEE International Workshop on Hardware-Oriented Security and Trust (HOST): 108-111 (2009).
  [Abstract | PDF]
• [CHES’09] Rajat Subhra Chakraborty, Francis Wolff, Somnath Paul, Christos Papachristou and Swarup Bhunia, “MERO: A Statistical Approach for Hardware Trojan Detection”. Cryptographic Hardware and Embedded Systems (CHES): 396-410 (2009).
  [Abstract | PDF]
  
• [EMBC’09] Seetharam Narasimhan, Hillel J. Chiel and Swarup Bhunia, “A Preferential Design Approach for Energy-Efficient and Robust Implantable Neural Signal Processing”. Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC): 6383-6386 (2009). [Student Best Paper Finalist].
  [Abstract | PDF]
• [TRANSDUCERS’09] Te-Hao Lee, Kevin M. Speer, Xiaoan Fu, Swarup Bhunia, and Mehran Mehregany, “Polycrystalline Silicon Carbide NEMS for High-Temperature Logic”. International Conference on Solid State Sensors and Actuators (TRANSDUCERS): 900-903 (2009).
  [Abstract | PDF]
  

2008

• [NMDC’08] Te-Hao Lee, Kevin M. Speer, Kenji Okino, Xiaoan Fu, Swarup Bhunia, and Mehran Mehregany, “Polycrystalline-SiC Nanoelectromechanical Switches for High-Temperature Switching and Logic Applications”. IEEE Nanotechnology and Device Conference (NMDC) (2008).
• [ICCAD’08] Rajat Subhra Chakraborty and Swarup Bhunia, “Hardware protection and authentication through netlist level obfuscation”. IEEE International Conference on Computer-Aided Design (ICCAD): 674-677 (2008).
  [Abstract | PDF]
• [ICCAD’08] Somnath Paul, Saibal Mukhopadhyay, and Swarup Bhunia, “Hybrid CMOS-STTRAM FPGA Design Optimization for Low Power and High Integration Density”. IEEE International Conference on Computer-Aided Design (ICCAD): 589-592 (2008).
  [Abstract | PDF]
• [EMBC’08] Seetharam Narasimhan, Miranda Cullins, Hillel Chiel, and Swarup Bhunia, “Wavelet-Based Neural Pattern Analyzer for Behaviorally Significant Burst Pattern Recognition”. Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC): 38-41 (2008).
  [Abstract | PDF]
• [HOST’08] Rajat Subhra Chakraborty, Somnath Paul, and Swarup Bhunia, “On-Demand Transparency for Improving Hardware Trojan Detectability”. IEEE International Workshop on Hardware-Oriented Security and Trust (HOST): 48-50 (2008).
  [Abstract | PDF]
• [DAC’08] Seetharam Narasimhan, Somnath Paul, and Swarup Bhunia, “Collective computing based on swarm intelligence”. Design Automation Conference (DAC): 349-350 (2008). [WACI (Wild & Crazy Ideas) Paper].
  [Abstract | PDF]
• [DAC’08] Somnath Paul and Swarup Bhunia, “Reconfigurable computing using content addressable memory for improved performance and resource usage”. Design Automation Conference (DAC): 786-791 (2008).
  [Abstract | PDF]
• [ISQED’08] Rajat Subhra Chakraborty and Swarup Bhunia, “Micropipeline-Based Asynchronous Design Methodology for Robust System Design Using Nanoscale Crossbar”. International Symposium on Quality Electronic Design (ISQED): 697-701 (2008).
  [Abstract | PDF]
• [GLSVLSI’08] Matthew Holtz, Seetharam Narasimhan, and Swarup Bhunia, “On-die CMOS voltage droop detection and dynamic compensation”. ACM Great Lakes Symposium on VLSI (GLSVLSI): 35-40 (2008).
  [Abstract | PDF]
• [ISQED’08] Yu Zhou, Somnath Paul, and Swarup Bhunia, “Towards Uniform Temperature Distribution in SOI Circuits Using Carbon Nanotube Based Thermal Interconnect”. International Symposium on Quality Electronic Design (ISQED): 861-866 (2008).
  [Abstract | PDF]
• [DATE’08] Lawrence Leinweber and Swarup Bhunia, “Fine-Grained Supply Gating Through Hypergraph Partitioning and Shannon Decomposition for Active Power Reduction”. Design, Automation and Test in Europe Conference (DATE): 373-378 (2008).
  [Abstract | PDF]
• [DATE’08] Yu Zhou, Somnath Paul and Swarup Bhunia, “Harvesting Wasted Heat in a Microprocessor Using Thermoelectric Generators: Modeling, Analysis and Measurement”. Design, Automation and Test in Europe Conference (DATE): 98-103 (2008).
  [Abstract | PDF]
• [DATE’08] Francis Wolff, Christos Papachristou, Rajat Subhra Chakraborty, and Swarup Bhunia, “Towards Trojan-Free Trusted ICs: Problem Analysis and Detection Scheme”. Design, Automation and Test in Europe Conference (DATE) : 1362-1365 (2008).
  [Abstract | PDF]
• [VLSID’08] Rajat Subhra Chakraborty, Somnath Paul, and Swarup Bhunia, “Analysis and Robust Design of Diode-Resistor Based Nanoscale Crossbar PLA Circuits”. International Conference on VLSI Design (VLSID): 441-446 (2008).
  [Abstract | PDF]
• [ASPDAC’08] Somnath Paul and Swarup Bhunia, “MBARC: A scalable memory based reconfigurable computing framework for nanoscale devices”. Asia and South Pacific Design Automation Conference (ASP-DAC): 77-82 (2008).
  [Abstract | PDF]

2007

• [BIOCAS’07] Seetharam Narasimhan, Yu Zhou, Hillel J. Chiel, and Swarup Bhunia, “Low-Power VLSI Architecture for Neural Data Compression Using Vocabulary-based Approach”. IEEE Biomedical Circuits and Systems Conference (BioCAS): 134-137 (2007).
  [Abstract | PDF]
• [ICCD’07] Somnath Paul and Swarup Bhunia, “Memory based computation using embedded cache for processor yield and reliability improvement”. IEEE International Conference on Computer Design (ICCD): 341-346 (2007).
  [Abstract | PDF]
• [ICCAD’07] Somnath Paul, Siva Krishnamurthy, Hamid Mahmoodi, and Swarup Bhunia, “Low-overhead design technique for calibration of maximum frequency at multiple operating points”. IEEE International Conference on Computer-Aided Design (ICCAD): 401-404 (2007).
  [Abstract | PDF]
• [ISLPED’07] Yu Zhou, Shijo Thekkel, and Swarup Bhunia, “Low power FPGA design using hybrid CMOS-NEMS approach”. IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED): 14-19 (2007).
  [Abstract | PDF]
• [IOLTS’07] Somnath Paul, Rajat Chakraborty, and Swarup Bhunia, “Defect-Aware Configurable Computing in Nanoscale Crossbar for Improved Yield”. IEEE Symposium on On-Line Testing (IOLTS): 29-36 (2007).
  [Abstract | PDF]
• [IOLTS’07] Swaroop Ghosh, Patrick N. Dai, Swarup Bhunia, and Kaushik Roy, “Tolerance to Small Delay Defects by Adaptive Clock Stretching”. IEEE Symposium on On-Line Testing (IOLTS): 244-252 (2007).
  [Abstract | PDF]
• [EMBS’07] Seetharam Narasimhan, Massood Tabib-Azar, Hillel J. Chiel, and Swarup Bhunia, “Neural Data Compression with Wavelet Transform: A Vocabulary Based Approach”. International IEEE/EMBS on Neural Engineering (EMBS): 666-669 (2007).
  [Abstract | PDF]
• [VTS’07] Somnath Paul, Rajat Subhra Chakraborty, and Swarup Bhunia, “VIm-Scan: A Low Overhead Scan Design Approach for Protection of Secret Key in Scan-Based Secure Chips”. IEEE VLSI Test Symposium (VTS): 455-460 (2007).
  [Abstract | PDF]
• [NANOTECH’07] Rajat Chakraborty, Seetharam Narasimhan, Swarup Bhunia, “Hybridization of CMOS With CNT-Based Nano-Electromechanical Switch for Low Leakage and Robust Circuit Design”. NSTI Nanotechnology Conference and Trade Show (NANOTECH): 2480-2488 (2007).
  [Abstract | PDF]
• [ISQED’07] Siva Krishnamurthy, Somnath Paul, and Swarup Bhunia, “Adaptation to Temperature-Induced Delay Variations in Logic Circuits Using Low-Overhead Online Delay Calibration”. International Symposium on Quality Electronic Design (ISQED): 755-760 (2007).
  [Abstract | PDF]
• [DATE’07] Swaroop Ghosh, Swarup Bhunia, and Kaushik Roy, “Low-overhead circuit synthesis for temperature adaptation using dynamic voltage scheduling”. Design, Automation and Test in Europe Conference (DATE): 1532-1537 (2007).
  [Abstract | PDF]
• [ASPDAC’07] Swarup Bhunia, Massood Tabib Azar, and Daniel Saab, “Ultralow-Power Reconfigurable Computing with Complementary Nano-Electromechanical Carbon Nanotube Switches”. Asia and South Pacific Design Automation Conference (ASP-DAC): 86-91 (2007).
  [Abstract | PDF]

2006

• [NANOARCH’06] Swarup Bhunia, Massood Tabib-Azar, and Daniel Saab, “Ultralow-Power Adaptive System Architecture Using Complementary Nano-Electromechanical Carbon Nanotube Switches”. IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) (2006).
  [Abstract | PDF]
• [SOC’06] Massood Tabib-Azar, Swarup Bhunia, and Daniel Saab, “Complimentary Nano-Electromechanical Carbon Nanotube Switches”. IEEE International System-on-Chip Conference (SoC)(2006).
  [Abstract | PDF]
• [ICCAD’06] Swaroop Ghosh, Swarup Bhunia, and Kaushik Roy, “CRISTA: A New Paradigm for Low-Power, Variation-Tolerant, and Adaptive Circuit Synthesis Using Critical Path Isolation”. IEEE International Conference on Computer-Aided Design (ICCAD): 1947-1956 (2006).
  [Abstract | PDF]
• [ASPDAC’06] Ashish Goel, Swarup Bhunia, Hamid Mahmoodi, and Kaushik Roy, “A Low-Overhead Design of Soft-Error-Tolerant Scan Flip-Flop with Enhanced-Scan Capability”. Asia and South Pacific Design Automation Conference (ASP-DAC): 665-670 (2006).
  [Abstract | PDF]
• [ASPDAC’06] Animesh Datta, Swarup Bhunia, Jung Hwan Choi, Saibal Mukhopadhyay, and Kaushik Roy, “Speed binning aware design methodology to improve profit under parameter variations”. Asia and South Pacific Design Automation Conference (ASP-DAC): 712-717 (2006). [Best Paper Nomination]. 
  [Abstract | PDF]
• [DATE’06] Nilanjan Banerjee, Swarup Bhunia, Hamid Mahmoodi, and Kaushik Roy, “Low power synthesis of dynamic logic circuits using fine-grained clock gating”. Design, Automation and Test in Europe Conference (DATE): 862-867 (2006).
  [Abstract | PDF]
• [IOLTS’06] Swaroop Ghosh, Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy, “Delay Fault Localization in Test-Per-Scan BIST Using Built-In Delay Sensor”. IEEE Symposium on On-Line Testing (IOLTS): 31-36 (2006).
  [Abstract | PDF]
• [DATE’06] Arijit Raychowdhury, Bipul Chandra Paul, Swarup Bhunia, Kaushik Roy, “Ultralow power computing with sub-threshold leakage: a comparative study of bulk and SOI technologies”. Design, Automation and Test in Europe Conference (DATE): 856-861 (2006).
  [Abstract | PDF]

2005

• [ISLPED’05] Amit Agarwal, Kunhyuk Kang, Swarup Bhunia, and Kaushik Roy, “Effectiveness of low power dual-V_t designs in nano-scale technologies under process parameter variations”. IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED): 14-19 (2005).
  [Abstract | PDF]
• [DAC’05] Swarup Bhunia, Hamid Mahmoodi, Nilanjan Banerjee, Qikai Chen, and Kaushik Roy, “A novel synthesis approach for active leakage power reduction using dynamic supply gating”. Design Automation Conference (DAC): 479-484 (2005).
  [Abstract | PDF]
• [VTS’05] Qikai Chen, Hamid Mahmoodi, Swarup Bhunia, and Kaushik Roy, “Analysis of New Fault Mechanisms and Test Methodologies for Failures in SRAM due to Process Variations”. IEEE VLSI Test Symposium (VTS) (2005).
  [Abstract | PDF]
• [IOLTS’05] Animesh Datta, Saibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy, “Yield Prediction of High Performance Pipelined Circuit with Respect to Delay Failures in Sub-100nm Technology”. IEEE Symposium on On-Line testing (IOLTS): 275-280 (2005).
  [Abstract | PDF]
• [ATS’05] Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, Kaushik Roy, “A Statistical Approach to Area-Constrained Yield Enhancement for Pipelined Circuits under Parameter Variations”. Asian Test Symposium (ATS): 170-175 (2005).
  [Abstract | PDF]
• [ATS’05] Swaroop Ghosh, Swarup Bhunia, Kaushik Roy, “Shannon Expansion Based Supply-Gated Logic for Improved Power and Testability”. Asian Test Symposium (ATS): 404-409 (2005).
  [Abstract | PDF]
• [DATE’05] Swarup Bhunia, Hamid Mahmoodi-Meimand, Arijit Raychowdhury, Kaushik Roy, “A Novel Low-overhead Delay Testing Technique for Arbitrary Two-Pattern Test Application”. Design, Automation and Test in Europe Conference (DATE): 1136-1141 (2005).
  [Abstract | PDF]
• [DATE’05] Saibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy, “Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits”. Design, Automation and Test in Europe Conference (DATE): 224-229 (2005).
  [Abstract | PDF]
• [ICCD’05] Nilanjan Banerjee, Arijit Raychowdhury, Swarup Bhunia, Hamid Mahmoodi-Meimand, Kaushik Roy, “Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis”. IEEE International Conference on Computer Design (ICCD): 206-214 (2005).
  [Abstract | PDF]
• [ISQED’05] Animesh Datta, Swarup Bhunia, Nilanjan Banerjee, Kaushik Roy, “A Power-Aware GALS Architecture for Real-Time Algorithm-Specific Tasks”. International Symposium on Quality Electronic Design (ISQED): 358-363 (2005).
  [Abstract | PDF]
• [ISQED’05] Swarup Bhunia, Hamid Mahmoodi-Meimand, Debjyoti Ghosh, Kaushik Roy, “Power Reduction in Test-Per-Scan BIST with Supply Gating and Efficient Scan Partitioning”. International Symposium on Quality Electronic Design (ISQED): 453-458 (2005).
  [Abstract | PDF]

2004

• [ISQED’04] Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy, “Frequency Specification testing of Analog Filters Using Wavelet Transform of Dynamic Supply Current“. IEEE International Symposium on Quality Electronic Design (ISQED): 389-394 (2004).
  [Abstract | PDF]
• [DFT’04] Swarup Bhunia, Hamid Mahmoodi-Meimand, Arijit Raychowdhury, Kaushik Roy, “First Level Hold: A Novel Low-Overhead Delay Fault Testing Technique”. IEEE International Symposium on Defect Tolerance in VLSI and Nanotechnology Systems (DFT): 314-315 (2004).
  [Abstract | PDF]
• [IOLTS’04] Debjyoti Ghosh, Swarup Bhunia, Kaushik Roy, “A Technique to Reduce Power and Test Application Time in BIST”. IEEE Symposium on On-Line Testing (IOLTS): 182-183 (2004).
  [Abstract | PDF]
• [ICCD’04] Swarup Bhunia, Hamid Mahmoodi, Saibal Mukhopadhyay, Debjyoti Ghosh, and Kaushik Roy, “A Novel Low Power Scan Design Technique Using Supply Gating”. IEEE International Conference on Computer Design (ICCD): 60-65 (2004). [Best Paper Award]
  [Abstract | PDF]
  
• [DATE’04] Swarup Bhunia, Arijit Raychowdhury, and Kaushik Roy, “Trim Bit Setting of Analog Filters Using Wavelet-Based Supply Current Analysis”. Design, Automation and Test in Europe Conference (DATE): 704-705 (2004).
  [Abstract | PDF]

2003

• [LATS’03] Swarup Bhunia and Kaushik Roy, “Defect Oriented Testing of Analog Circuits Using Wavelet Analysis of Dynamic Supply Current”. Latin American Test Symposium (LATS) (2005). [Best Paper Award]
  [Abstract | PDF]
• [DFT’03] Debjyoti Ghosh, Swarup Bhunia, and Kaushik Roy, “Multiple Scan Chain Design Technique for Power Reduction during Test Application in BIST”. IEEE International Symposium on Defect Tolerance in VLSI and Nanotechnology Systems (DFT): 191-198 (2003).
  [Abstract | PDF]
• [HPCA’03] Hai Li, Swarup Bhunia, Yiran Chen, Kaushik Roy, and T. N. Vijaykumar. “Deterministic Clock Gating for Microprocessor Power Reduction”. IEEE Symposium on High-Performance Computer Architecture (HPCA): 113-122 (2003).
  [Abstract | PDF]
• [DATE’03] Lih-yih Chiou, Swarup Bhunia, and Kaushik Roy, “Synthesis of Application-Specific Highly-Efficient Multi-Mode Systems for Low-Power Applications”. Design, Automation and Test in Europe Conference (DATE): 10096-10103 (2003).
  [Abstract | PDF]

2002

• [DATE’02] Swarup Bhunia and Kaushik Roy, “Fault Detection and Diagnosis Using Wavelet Based Transient Current Analysis”. Design, Automation and Test in Europe Conference (DATE): 1118 (2002).
  [Abstract | PDF]
• [VTS’02] Swarup Bhunia and Kaushik Roy, “Dynamic Supply Current Testing of Analog Circuits Using Wavelet Transform”. IEEE VLSI Test Symposium (VTS): 302-310 (2002).
  [Abstract | PDF]
• [DAC’02] Swarup Bhunia, Kaushik Roy and Jaume Segura “A novel wavelet transform based transient current analysis for fault detection and localization”. Design Automation Conference (DAC): 361-366 (2002).
  [Abstract | PDF]
• [ATS’02] Swarup Bhunia, Hai Li, and Kaushik Roy, “Gated-Ground Cache: A High Performance I_DDQ-Testable Cache for Scaled CMOS Technologies”. IEEE Asian Test Symposium (ATS): 157-162 (2002).
  [Abstract | PDF]

2000

• [VLSID’00] Swarup Bhunia, Subhasish Majumdar, Ayon Sirkar, and Susmita Sur-kolay, “Topological Routing Amidst Polygonal Obstacles”. International Conference on VLSI Design (VLSID): 274-279 (2000).
  [Abstract | PDF]

1999

• [VLSID’99] Swarup Bhunia, Soumya Ghosh, Pramod Kumar, Partha Das, and Jayanta Mukherjee, “Design, Simulation and Synthesis of an ASIC for Fractal Image Compression”. International Conference on VLSI Design(VLSID): 544-547 (1999).
  [Abstract | PDF]

2026

• [VTS’26] Sudipta Paria, Aritra Dasgupta, and Swarup Bhunia, “Exploring Agentic LLM Paradigms for Hardware Verification across Abstraction Levels”. to appear in IEEE VLSI Test Symposium (VTS) (2026). [Invited Full Paper]
• [FPGA’26] Aritra Dasgupta, Jonathan Cruz, Peyman Deghanzadeh, Pravin Gaikwad, Sudipta Paria, and Swarup Bhunia, “PROM: Protection against Reverse Engineering Attacks through Programmable Logic Macros”.  34th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA) (2026). [One-Page Abstract]
• [ISQED’26] Habibur Rahaman, Sudipta Paria, and Swarup Bhunia, “Evolving Landscape of Attacks on AI Hardware and Robust Defenses”, to appear in Special Session on “Security for AI and AI for Security”, in the 27^th International Symposium on Quality Electronic Design (ISQED) (2026). 
• [GOMACTECH’26] Mahmudul Hasan, Tamzidul Hoque, Sudipta Paria, and Swarup Bhunia, “A Statistical Approach to Detecting Trojans in COTS Hardware Using Microarchitectural Events”. Government Microcircuit Applications & Critical Technology (GOMACTech) (2026).
• [GOMACTECH’26] Habibur Rahaman, Atri Chatterjee, and Swarup Bhunia, “SAMURAI: Runtime Attack Detection in AI Accelerators Using AI Performance Counters”. Government Microcircuit Applications & Critical Technology (GOMACTech) (2026).
• [GOMACTECH’26] Raghul Saravanan, Sai Manoj Pudukotai Dinakarrao, Sudipta Paria, Aritra Dasgupta, and Swarup Bhunia, Intelligent Graybox Fuzzing via ATPG-Guided Seed Generation and Submodule Analysis”. Government Microcircuit Applications & Critical Technology (GOMACTech) (2026).
• [GOMACTECH’26] Tambiara Tabassum, Dinesh Reddy Ankireddy, Sudipta Paria, Sandip Ray, and Swarup Bhunia, “A System-on-Chip Instrumentation Architecture for Efficient Post-Silicon Fuzzing”. Government Microcircuit Applications & Critical Technology (GOMACTech) (2026).
• [GOMACTECH’26] Atri Chatterjee, Habibur Rahaman, and Swarup Bhunia, “ASTRA: Automated Insertion of Distributed Entropy Sources for Robust Authentication”. Government Microcircuit Applications & Critical Technology (GOMACTech) (2026).
• [GOMACTECH’26] Tanzim Mahfuz, Tasneem Suha, Prabuddha Chakraborty, Sudipta Paria, and Swarup Bhunia, “XAI Enabled Power Side-Channel Estimation & Mitigation in Sensitive Digital Hardware”. Government Microcircuit Applications & Critical Technology (GOMACTech) (2026).

2025

• [CODES+ISSS’25] Atri Chatterjee, Habibur Rahman, and Swarup Bhunia, “MARVEL-PUF: A Robust Multi-Bit Memory PUF for FPGA-based Embedded Systems Security”. International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) (2025).
  [Abstract | PDF]
• [ASEE’25] Woorin Hwang, Andrea Ramirez-Salgado, Rohan Reddy Kalavakonda, Yessy Eka Ambarwati, Pavlo Antonenko, and Swarup Bhunia, “WIP: Empowering First-Year Engineering Students for Career Choices through Hands-On AI Hardware Experiences”. ASEE Annual Conference & Exposition (ASEE)(2025).
  [Abstract | PDF]
• [ASEE’25] Andrea Ramirez-Salgado, Swarup Bhunia, and Pavlo Antonenko, “Empowering Future Engineers: An Inclusive Curriculum for AIoT and Intelligent Embedded Systems”. ASEE Annual Conference & Exposition (ASEE) (2025).
  [Abstract | PDF]
• [GOMACTECH’25] Sudipta Paria, Aritra Dasgupta, and Swarup Bhunia, “Post-Silicon Hardware Trojan Detection with High Confidence Leveraging Automated Test Patterns”. Government Microcircuit Applications & Critical Technology (GOMACTech) (2025).
• [GOMACTECH’25] Emmanuel Elias, Tambiara Tabassum, Kshitij raj, Atri Chatterjee, Swarup Bhunia, and Sandip ray, “MCSE: A Low-Cost Security Engine for Protecting Edge Devices Against Supply-Chain Attacks”. Government Microcircuit Applications & Critical Technology (GOMACTech) (2025).
• [GOMACTECH’25] Tanzim Mahfuz, Prabuddha Chakraborty, and Swarup Bhunia, “X-DFS: Explainable Artificial Intelligence Guided Design-for-Security Solution Space Exploration”. Government Microcircuit Applications & Critical Technology (GOMACTech) (2025).
  [Abstract | PDF]
• [GOMACTECH’25] Aritra Dasgupta, Sudipta Paria, Swarup Bhunia, and Christopher Sozio, and Andrew Lukefahr, “Library-Attack: Reverse Engineering Approach for Evaluating Hardware IP Protection”. Government Microcircuit Applications & Critical Technology (GOMACTech) (2025).
  [Abstract | PDF]

2024

• [ISQED’24] Kshitij Raj, Aritra Bhattacharyay, Swarup Bhunia, Sandip Ray: “Trimming The Fat: A Minimum-Security Architecture for Protecting SoC Designs Against Supply Chain Threats”. International Symposium on Quality Electronic Design (ISQED) (2024). [One-page Abstract]
  [Abstract | PDF]
• [GOMACTECH’24] Andrea Ramirez-Salgado, Tanvir Hossain, Swarup Bhunia, Pavlo Antonenko, “Board 393: Supporting Hardware Engineering Career Choice in First-Year Engineering Students”. Government Microcircuit Applications & Critical Technology (GOMACTech) (2024).
  [Abstract | PDF]
• [GOMACTECH’24] Kshitij raj, Atri Chatterjee, Swarup Bhunia, and Sandip ray, “A Security engine Solution for Protecting SoC designs Against Supply-Chain Threats”. Government Microcircuit Applications & Critical Technology (GOMACTech) (2024).
• [GOMACTECH’24] Mahmudul Hasan, Tamzidul Hoque, Sudipta Paria and Swarup Bhunia, “A Statistical Approach to Detecting Trojans in COTS Hardware Using Microarchitectural Events”. Government Microcircuit Applications & Critical Technology (GOMACTech) (2024).
• [GOMACTECH’24] Christopher vega, Patanjali SlPSK, Ravalika Karnati, and Swarup Bhunia, “VARI-CHECK: Authentication of CoTS devices using ML-Based variability Characterization”. Government Microcircuit Applications & Critical Technology (GOMACTech) (2024).
• [GOMACTECH’24] Aritra Dasgupta, Jackson Fugate, Greg Stitt, Swarup Bhunia, Nij Dorairaj, and David Kehlet, “RIPPER: Low-overhead Fine-grain redaction Tool Flow for hardware IP Protection”. Government Microcircuit Applications & Critical Technology (GOMACTech) (2024).

2023

• [GOMACTECH’23] Maneesh Merugu, Md Moshiur Rahman, Aritra dasgupta, Swarup Bhunia, and Sandip Ray, “Formal equivalence checking for locked and Redacted Hardware designs”. Government Microcircuit Applications & Critical Technology (GOMACTech) (2023).
• [GOMACTECH’23] Christopher vega, Patanjali SLPSK, and Swarup Bhunia, “IOLock: An Input/Output Protection Scheme for Chip and PCB Protection”.  Government Microcircuit Applications & Critical Technology (GOMACTech) (2023).
  [Abstract | PDF]
• [GOMACTECH’23] Aritra dasgupta, Md Moshiur Rahman, Patanjali SLPSK, and Swarup Bhunia, “Low-overhead Hardware Redaction Using Bitstream Compaction”. Government Microcircuit Applications & Critical Technology (GOMACTech) (2023).
• [GOMACTECH’23] Rasheed Almawzan, Reiner Dizon-Paradis, Aritra dasgupta, Dipal Halder, Md Moshiur Rahman, Maneesh Merugu, Sandip Ray, and Swarup Bhunia, “OASIS: A Layered IP Protection Framework for Structured ASIC”. Government Microcircuit Applications & Critical Technology (GOMACTech) (2023).
• [GOMACTECH’23] Jackson Fugate, Greg Stitt, Naren vikram Raj Masna, Aritra Dasgupta, and Swarup Bhunia, “ATPG and Test Methods for Redacted IP”. Government Microcircuit Applications & Critical Technology (GOMACTech) (2023).
  [Abstract | PDF]
• [GOMACTECH’23] Andrea Ramirez-Salgado, Tanvir Hossain, Tamzidul Hoque, Swarup Bhunia, Mary Koroly, Bradford Davey, Pavlo Antonenko, “Board 265: Engaging Students in Exploring Computer Hardware Fundamentals Using FPGA Board Games”. Government Microcircuit Applications & Critical Technology (GOMACTech) (2023).
  [Abstract | PDF]

2020

• [GOMACTECH’20] Tamzidul Hoque, Shuo Yang, Aritra Bhattacharya, Jonathan W Cruz, and Swarup Bhunia, “An Automated Framework for Board-level Trojan Benchmarking”. Government Microcircuit Applications & Critical Technology (GOMACTech) (2020).
  [Abstract | PDF]
• [GOMACTECH’20] Jonathan W Cruz, Abhishek Nair, Tamzidul Hoque, Prabuddha Chakraborty, Pravin Gaikwad, Naren Masna, and Swarup Bhunia, Brian Dupaix, and Waleed Khalil, “MIMIC: A Machine Intelligence Based Trojan Benchmarking Framework”. Government Microcircuit Applications & Critical Technology (GOMACTech) (2020).
• [Abstract | PDF]
• [GOMACTECH’20] Moshiur Rahman, Travis Meade, Yier Jin, and Swarup Bhunia, “You Break I Fix: A Collaborative Approach for Strengthening Sequential Obfuscation of Hardware Intellectual Property”. Government Microcircuit Applications & Critical Technology (GOMACTech) (2020).
  [Abstract | PDF]
• [GOMACTECH’20] Chris Taylor, Swarup Bhunia, Brian Dupaix, and Waleed Khalil, “A Structural Analysis of Logic Locking”. Government Microcircuit Applications & Critical Technology (GOMACTech) (2020).
• [GLSVLSI’20] Tamzidul Hoque, Patanjali SLPSK, and Swarup Bhunia, “Trust Issues in COTS: The Challenges and Emerging Solution”. ACM Great Lakes Symposium on VLSI (GLSVLSI): 211-216 (2020)
  [Abstract | PDF]
• [HOST’20] Domenic Forte, Swarup Bhunia, Ramesh Karri, Jim Plusquellic and Mark Tehranipoor, “IEEE International Symposium on Hardware Oriented Security and Trust (HOST): Past, Present, and Future“. IEEE International Symposium on Hardware Oriented Security and Trust (HOST): 1-4 (2020)
  [Abstract | PDF]
  

2019

• [TECHON’19] Prabuddha Chakraborty and Swarup Bhunia, “HASTE: Software Security Analysis for Timing Attacks on Clear Hardware Assumption”. SRC TECHCON (TECHCON) (2019).
  [Abstract | PDF]
• [TECHON’19] Atul Prasad Debnath, Swarup Bhunia, and Sandip Ray, “A Flexible Architecture for Systematic Implementation of SoC Security Policies”. SRC TECHCON (TECHCON) (2019).
• [VTS’19] Nagmeh Karimi, Jeyavijayan Rajendran, Hassan Salmani, Tamzidul Hoque, and Swarup Bhunia, “Special Session: Countering IP Security threats in Supply chain”. IEEE VLSI Test Symposium (VTS): 1-9 (2019).
  [Abstract | PDF]
• [DAC’19] Jonathan Cruz, Prabhat Mishra, and Swarup Bhunia, “The Metric Matters: The Art of Measuring Trust in Electronics”. Design Automation Conference (DAC): 222 (2019).
  [Abstract | PDF]
• [ICCE’19] Shuo Yang, Abdulrahman Alaql, Tamzidul Hoque, and Swarup Bhunia, “Runtime Integrity Verification in Cyber-physical Systems using Side-Channel Fingerprint”. IEEE International Conference on Consumer Electronics (ICCE): 1-6 (2019).
  [Abstract | PDF]
• [GOMACTECH’19] Atul Prasad Debnath, Srivalli Boddupalli, Swarup Bhunia, and Sandip Ray, “ARK: Architecture for Security Resiliency in SoC Designs with NetworK-on-Chip (NoC) Fabrics”. Government Microcircuit Applications & Critical Technology (GOMACTech) (2019).
  [Abstract | PDF]

2018

• [TECHCON’18] Tamzidul Hoque and Swarup Bhunia, “A Systematic Machine Learning Framework for IP Trust Verification”. SRC TECHCON (TECHCON), Austin, TX, USA, Sept 2018.
• [GOMACTECH’18] Daniel Capecci, Gustavo Contreras, Domenic Forte, Mark Tehranipoor, and Swarup Bhunia, “Automated SoC Security from Design to Fabrication”. Government Microcircuit Applications & Critical Technology (GOMACTech) (2018).

2017

• [GLSVLSI’17] Sarah Amir, Bicky Shakya, Domenic Forte, Mark Tehranipoor, and Swarup Bhunia, “Comparative Analysis of Hardware Obfuscation for IP Protection”. ACM Great Lakes Symposium on VLSI (GLSVLSI): 363-368 (2017)
  [Abstract | PDF]
• [HILTON-HEAD’17] [Abstract & Poster Presentation] Cheng Chen, Swarup Bhunia, Soumyajit Mandal and Fengchao Zhang, “Broadband Quantitative NQR Analysis of Medicines and Nutritional Supplements, Practical Applications of NMR in Industry Conference (PANIC), Hilton Head Island, USA, 2017.
  [Abstract | PDF] 
• [TECHCON’17] Tamzidul Hoque, Prabhat Mishra, and Swarup Bhunia, “A Systemic Feature Extraction Methodology for Machine Learning Based Hardware Trojan Detection”. SRC TECHCON (TECHCON), Austin, TX, USA, Sept 2017.
• [TECHCON’17] Atul Prasad Debnath, Sandip Ray, and Swarup Bhunia, “An Adaptable System-on-Chip Security Architecture for Internet of Things Applications”. SRC TECHCON (TECHCON), Austin, TX, USA, Sept 2017.
  [Abstract ]

2016

• [ICCD’16] Sandip Ray, Tamzidul Hoque, Abhishek Basak, and Swarup Bhunia, “The power play: Security-energy trade-offs in the IoT regime”. IEEE International Conference on Computer Design (ICCD): 690-693(2016)
  [Abstract | PDF]
  
• [FPGA’16] Wenchao Qian, Christopher Babecki, Robert Karam, and Swarup Bhunia, “ENFIRE: An Energy-efficient Fine-grained Spatio-temporal Reconfigurable Computing Fabric” (Abstact Only). ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA): 275 (2016). [One-page Abstract]
  [Abstract | PDF]
• [TECHCON’16] Fengchao Zhang, Abhishek Basak, Sandip Ray, and Swarup Bhunia, “Design-for-Debug Architecture Enhances SoC Security”. SRC TECHCON (TECHCON), Austin, TX, USA, Sept 2016.
  [Abstract | PDF]
• [TECHCON’16] Robert Karam and Swarup Bhunia, “Energy-Efficient Memory-Centric Reconfigurable Accelerator for Data Intensive Analytics”. SRC TECHCON (TECHCON), Austin, TX, USA, Sept 2016.
  [Abstract | PDF]
• [TECHCON’16] Tamzidul Hoque, Robert Karam, and Swarup Bhunia, “Protection of IPs Mapped to FPGAs against Malicious Hardware”. SRC TECHCON (TECHCON), Austin, TX, USA, Sept 2016.
• [VTS’16] Sandip Ray, Swarup Bhunia, Yier Jin, and Mark Tehranipoor, “Security validation in IoT space”. IEEE VLSI Test Symposium (VTS): 1 (2016)
  [Abstract | PDF]
• [GLSVLSI’16] Robert Karam, Rui Liu, Pai-Yu Chen, Shimeng Yu, and Swarup Bhunia, “Security Primitive Design with Nanoscale Devices: A Case Study with Resistive RAM”. ACM Great Lakes Symposium on VLSI (GLSVLSI): 299-304 (2016).
  [Abstract | PDF]  
  
• [EUS’16] Robert Karam, Steve Majerus, Swarup Bhunia, Steven Brose, Margot S. Damaser, and Dennis Bourbeau, “Autonomous closed-loop genital nerve stimulation identifies and inhibits hyper-reflexic bladder contractions”. Engineering and Urology Society (EUS) (2016).

2015

• [DAC’15] Sandip Ray, Jin Yang, Abhishek Basak, and Swarup Bhunia, “Correctness and Security and Odds: Post-silicon Validation of Modern SoC Designs”. Design Automation Conference (DAC) (2015). [Invited article in Special Session on “SoC Security Validation”]. [Invited Full Paper]
  [Abstract | PDF]
  
• [TECHCON’15] Abhishek Basak, Sandip Ray, and Swarup Bhunia, “A Centralized Flexible Infrastructure for Systematic Implementation of SoC Security Policies”, SRC TECHCON (TECHCON), Austin, TX, USA, Sept 2015.
  [Abstract | PDF]
• [EUS’15] Irene Makovey, Robert Karam, Steve Majerus, Dennis Bourbeau, Hui Zhu, Swarup Bhunia, Margot S. Damaser, “Event Detection Algorithm in Single Channel Bladder Pressure Recording”. Engineering and Urology Society (EUS) (2015).
  [Abstract | PDF]
• [MWSCAS’15] Robert Karam, Kai Yang, and Swarup Bhunia, “Energy-efficient reconfigurable computing using Spintronic memory”.  IEEE International Midwest Symposium on Circuits and Systems (MWSCAS): 1-4 (2015).
  [Abstract | PDF]
• [ICM’15] Robert Karam, Dennis Bourbeau, Steve Majerus, Iryna Makovey, Howard B. Goldman, Margot S. Damaser, and Swarup Bhunia, “Real-Time Contraction Event Detection from Bladder Pressure Recordings for Effective Diagnosis and Treatment of Urinary Incontinence”. Innovating for Continence Meeting (ICM) (2015).
  [Abstract | PDF]

2014

• [ICICDT’14] Somnath Paul, Saibal Mukhopadhyay, and Swarup Bhunia, “Robust low-power reconfigurable computing with a variation-aware preferential design approach”. IEEE International Conference on Integrated Circuit Design and Technology (ICICDT) : 1-6 (2014).
  [Abstract | PDF]
• [DATE’14] Swarup Bhunia, Vaishnavi Ranganathan, Tina He, Srihari Rajgopal, Rui Wang, Mehran Mehregany and Philip Feng, “Toward ultralow-power computing at exteme with silicon carbide (SiC) nanoelectromechanical logic”. Design, Automation and Test in Europe Conference (DATE): 1-6 (2014).
  [Abstract | PDF]
• [DATE’14] Somnath Paul, Robert Karam, Swarup Bhunia, and Ruchir Puri, “Energy-efficient hardware acceleration through computing in the memory”. Design, Automation and Test in Europe Conference (DATE): 1-6 (2014).
  [Abstract | PDF]

2013

• [MTV’13] Swarup Bhunia and Abhishek Basak, “Secure and Trusted SoC: Challenges and Emerging Solutions”. International Workshop on Microprocessor Test and Verification (MTV): 29-34 (2013).
  [Abstract | PDF]
• [MWSCAS’13] Abhishek Basak, Yu Zheng, Jangwon Park, Jongsun Park, and Swarup Bhunia, “Reconfigurable ECC for adaptive protection of memory”.  IEEE International Midwest Symposium on Circuits and Systems (MWSCAS): 1085-1088 (2013).
  [Abstract | PDF]

2011

• [ICCD’11] Xinmu Wang, Seetharam Narasimhan, Aswin Krishna, Tatini Mal-Sarkar, and Swarup Bhunia, “Sequential Hardware Trojan Attacks: Experiences from ESC 2010”. 29th IEEE International Conference on Computer Design (ICCD) (2011). [Special session “Capture the Chip”] [Invited Full Paper]
  [Abstract | PDF]
• [MWSCAS’11] Hadi Hajimiri, Somnath Paul, Anandaroop Ghosh, Swarup Bhunia, and Prabhat Mishra, “Reliability Improvement in Many-Core Architectures through Computing in Embedded Memory”. IEEE International Midwest Symposium on Circuits and Systems (MWSCAS) (2011). [Special session on self-healing circuits in scaled technologies]. [Invited Full Paper]
  [Abstract | PDF]
• [FPGA’11] Somnath Paul and Swarup Bhunia, “Memory based computing: reshaping the fine-grained logic in a reconfigurable framework”. ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA): 283 (2011). [One-page Abstract]
  [Abstract | PDF]
• [TFMN’11] Srihari Rajgopal, Philip X.-L. Feng, Swarup Bhunia and Mehran Mehregany, “Nano Manufacturing of SiC Circuits — Nanomechanical Logic and NEMS-JFET Integration”. Technologies for Future Micro-Nano Manufacturing Workshop (TFMN) (2011). [Invited 2-page abstract]

2010

• [ASQED’10] Seetharam Narasimhan, Jongsun Park, and Swarup Bhunia, “Digital Signal Processing in Bio-implantable Systems: Design Challenges and Emerging Solutions”. Asia Symposium on Quality Electronic Design (ASQED) (2010). [Invited paper in special session on bio-sensing and bio-system design]. [Invited Full Paper]
  [Abstract | PDF]
• [VTS’10] Swarup Bhunia and Anand Raghunathan, “Special session 11B: Hot topic hardware security: Design, test and verification issues”. IEEE VLSI Test Symposium (VTS): 349 (2010).
  [Abstract | PDF]

2009

• [HLDVT’09] Rajat Subhra Chakraborty, Seetharam Narasimhan, and Swarup Bhunia, “Hardware Trojan: Threats and emerging solutions”. IEEE International High-Level Design Validation and Test Workshop (HLDVT): 166-171 (2009).
  [Abstract | PDF]
• [NANOARCH’09] Somnath Paul and Swarup Bhunia, “Computing with nanoscale memory: Model and architecture”. IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH): 1-6 (2009).
  [Abstract | PDF]

2008

• [ISLPED’08] Swarup Bhunia and Kaushik Roy, “Low power design under parameter variations”. IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED): 137-138 (2008).
  [Abstract | PDF]

2007

• [ITC’07] Swarup Bhunia and Kaushik Roy, “Power dissipation, variations and nanoscale CMOS design: Test challenges and self-calibration/self-repair solutions”. International Test Conference (ITC): 1-10 (2007).
  [Abstract | PDF]
• [VLSID’07] Swarup Bhunia, Saibal Mukhopadhyay, and Kaushik Roy, “Process Variations and Process-Tolerant Design”. International Conference on VLSI Design (VLSID): 699-704 (2007).
  [Abstract | PDF]

2026

• Swarup Bhunia and Mark M. Tehranipoor, “Hardware Security: A Hands-on Learning Approach”, Elsevier, Morgan Kaufmann, [Text Book] 2^nd Edition, USA, in press, to be published in April 2026.
  [Article]

2018

• Swarup Bhunia and Mark M. Tehranipoor, “Hardware Security: A Hands-on Learning Approach”, Elsevier, Morgan Kaufmann, [Text Book] 1^st Edition, USA, November, 2018.
  [Article]

2017

• Sandip Ray, Abhishek Basak, and Swarup Bhunia, “Security Policy in System-on-Chip – Specification, Implementation and Verification”, Springer USA, December, 2017.
  [Article]
• Swarup Bhunia and Mark M. Tehranipoor (Eds.), “The Hardware Trojan War: Attacks, Myths, and Defenses”, Springer, New York, USA, December 2017.
  [Article]
• Swarup Bhunia, Sandip Ray, and Susmita Sur-Kolay (Eds.), “Fundamentals of IP and SoC Security: Design, Verification and Debug”, Springer, New York, USA, May 2017.
  [Article]

2016

• Mark M. Tehranipoor, Domenic Forte, Garrett S. Rose, and Swarup Bhunia (Eds.), “Security Opportunities in Nano Devices and Emerging Technologies”, CRC Press, USA, December 2016.
  [Article]
• Prabhat Mishra, Swarup Bhunia, and Mark M. Tehranipoor (Eds.), “Hardware IP Security and Trust: Design, Validation, and Test Perspective”, Springer, New York, USA, October 2016.
  [Article]
• Domenic Forte, Swarup Bhunia, and Mark M. Tehranipoor (Eds.), “Hardware Protection through Obfuscation”, Springer, New York, USA, November 2016.
  [Article]

2014

• Swarup Bhunia, Steve Majerus, and Mohamad Sawan (Eds.), “Implantable Biomedical Microsystems: Design Principles and Applications”, Elsevier, MA, USA, January 2014.
  [Article]

2013

• Somnath Paul and Swarup Bhunia, “Computing with Memory for Energy-Efficient Robust Systems”, Springer, New York, USA, August 2013.
  [Article]

2010

• Swarup Bhunia and Saibal Mukhopadhyay (Eds.), “Low-Power Variation-Tolerant Design in Nanometer Silicon”, Springer, New York, USA, 1^st Edition, ISBN: 978-1-4419-7417-4, November 2010.
  [Article]

2025

• Moshiur Rahaman and Swarup Bhunia, “Hardware Obfuscation and Logic Locking”. Encyclopedia of Cryptography, Security and Privacy, Springer Nature Switzerland, Pages: 1069-1072, 2025.
  [Article]

2020

• Rajat Shubhra Chakraborty, Pranesh Pranesh Santikellur, and Swarup Bhunia, “Register Transfer Level Hardware Obfuscation”. “Behavioral Synthesis for Hardware Security”, edited by Srinivas Katkoori and Sheikh Ariful Islam, Springer, 2020.
  [Article]
• Abdulrahman M Alaql, Moshiur Rahman, Tamzidul Hoque, and Swarup Bhunia, “Hardware IP Protection through Obfuscation”. “Frontiers in Hardware Security and Trust”, IET (Institution of Engineering and Technology), edited by Chang Chip Hong (Editor), 2020.
  [Article]

2018

• Atul Prasad Debnath, Tamzidul Hoque, and Swarup Bhunia, “System-on-chip security architecture for internet of things”. “Security and Fault tolerance in Internet of Things“, Springer, 2018, Edited by Rajat Subhra ChakrabortyJimson MathewAthanasios V. Vasilakos.
  [Article]
• Swarup Bhunia, and Mark Tehranipoor, “Emerging Trend, Industrial Practices, New Attacks”. “The Hardware Trojan War: Attacks, Myths, and Defenses”, Springer, edited by Swarup Bhunia, and Mark Tehranipoor, 2018.
  [Article]
• Swarup Bhunia, and Mark Tehranipoor, “Hardware Trojan Preliminaries”. “The Hardware Trojan War: Attacks, Myths, and Defenses”, Springer, edited by Swarup Bhunia, and Mark Tehranipoor, 2018.
  [Article]

2017

• Fahim Rahman, Atul Prasad Deb Nath, Domenic Forte, Swarup Bhunia, and Mark Tehranipoor, “Composition of Physical Unclonable Functions: From Device to Architechture”. “Security Opportunities in Nano Devices and Emerging Technologies”, Springer, edited by Mark Tehranipoor, Domenic Forte, Garrett S. Rose and Swarup Bhunia, December 2017.
  [Article]
• Fahim Rahman, Atul Prasad Deb Nath, Domenic Forte, Swarup Bhunia, and Mark Tehranipoor, “Nano CMOS Logic-Based Security Primitive Design”. “Security Opportunities in Nano Devices and Emerging Technologies”, Springer, edited by Mark Tehranipoor, Domenic Forte, Garrett S. Rose and Swarup Bhunia, December 2017.
  [Article]
• Swarup Bhunia, Sandip Ray, and Susmita Sur-Kolay, “SoC Security: Summary and Future Directions”. “Fundamentals of IP and SoC Security: Design, Verification and Debug”, Springer, edited by Swarup Bhunia, Sandip Ray, and Susmita Sur-Kolay, NY, USA, 2017.
  [Article]
• Swarup Bhunia, Sandip Ray, and Susmita Sur-Kolay, “The Landscape of SoC and IP Security”. “Fundamentals of IP and SoC Security: Design, Verification and Debug”, edited by Swarup Bhunia, Sandip Ray, and Susmita Sur-Kolay, Springer, NY, USA, 2017.
  [Article]

2016

• Rajat Subhra Chakraborty and Swarup Bhunia, “State Space Obfuscation for Hardware IP Protection”. “Hardware Protection through Obfuscation”, edited by Domenic Forte, Swarup Bhunia, and Mark Tehranipoor, Springer, 2016.
  [Article]
• Prabhat Mishra, Mark Tehranipoor, and Swarup Bhunia, “Security and Trust Vulnerabilities in Third-party IPs”. “Hardware IP Security and Trust: Design, Validation, and Test Perspective”, edited by Prabhat Mishra, Swarup Bhunia, and Mark Tehranipoor, Springer, 2016.
  [Article]
• Robert Karam and Swarup Bhunia, “Compute-in-Memory Architecture for Data-Intensive Kernels”. “Emerging Technology and Architecture for Big-data Analytics”, edited by Hao Yu, Chip Hong Chang, and Anupam Chattopadhyay, Springer, 2016.
  [Article]
• Sandip Ray, Swarup Bhunia, and Prabhat Mishra, “Security Validation in System-on-Chip”. “Fundamentals of IP and SoC Security: Design, Verification, and Debug”, edited by Swarup Bhunia, Sandip Ray, and Susmita Sur-Kolay, Springer, NY, USA, December 2016.
  [Article]

2015

• Rajat Subhra Chakraborty, Yu Zheng, and Swarup Bhunia, “Obfuscation-based SoC Design for Security against Piracy and Trojan Attacks”. “Secure System Design and Trustable Computing”, edited by Chang Chip Hong and Miodrag Potkonjak, Springer International Publishing AG, Gewerbestrasse 11, 6330 Cham, Switzerland, 2015.
  [Article]
• Abhishek Basak and Swarup Bhunia, “Implantable Imager for Online Monitoring of Internal Organs”. “Bioimplantable Systems: Design Principles and Applications”, edited by Swarup Bhunia, Steve Majerus, and Mohamad Sawan, Elsevier, MA, USA, February 2015.
  [Article]

2013

• Abhishek Basak, Vaishnavi Ranganathan, Seetharam Narasimhan, and Swarup Bhunia, “Neural pattern recognition for closed-loop neuro-prosthesis”. “Implantable Bioelectronics – Devices, Materials and Applications”, edited by Evgeny Katz, Wiley-VCH, August 2013.
  [Article]

2012

• Swarup Bhunia and Seetharam Narasimhan, “Ultralow Power Implantable Electronics”. “Handbook of Energy-Aware and Green Computing”, edited by Sanjay Ranka and Ishfaq Ahmad, Chapman & Hall/CRC Press, January 2012, ISBN: 978-1439850404.
  [Article]

2011

• Swarup Bhunia and Seetharam Narasimhan, “Hardware Trojan Detection”. “Introduction to Hardware Security and Trust”, edited by Mohammad Tehranipoor and Cliff Wang, Springer, New York, USA, September 2011, ISBN: 978-1441980793.
  [Article]

2009

• Swarup Bhunia and Kaushik Roy, “Low Power Design Techniques and Test Implications”. “Power-Aware Testing and Test Strategies for Low Power Devices“, edited by Patrick Girard, Nicola Nicolici, and Xiaoqing Wen, Springer, New York, USA, 1^st Edition, ISBN: 978-1441909275, August 2009. [Best-seller in International Test Conference 2009].
  [Article]

2024

• Shivam Bhasin, Anupam Chattopadhyay, Tim Güneysu, Swarup Bhunia: Special Issue on Postquantum Cryptography for Internet of Things. IEEE Des. Test 41(5): 5-6 (2024).
  [Article]

2020

• Hai Helen Li, Wei Zhang, Swarup Bhunia, Wujie Wen, Introduction to the Special Issue on New Trends in Nanoelectronic Device, Circuit, and Architecture Design, Part 1. ACM J. Emerg. Technol. Comput. Syst. 16(3): 24:1-24:3 (2020).
  [Article]
• Wei Zhang, Hai Helen Li, Wujie Wen, Swarup Bhunia, Guest Editorial: ACM JETC Special Issue on New Trends in Nanolectronic Device, Circuit, and Architecture Design: Part 2. ACM J. Emerg. Technol. Comput. Syst. 16(4): 35:1-35:3 (2020).
  [Article]

2019

• Prabhat Mishra, Debdeep Mukhopadhyay, and Swarup Bhunia, “Guest Editorial: Special Section on Autonomous Intelligence for Security and Privacy Analytics”. IEEE Transacations on VLSI(TVLSI), Dec 2019.
  [Article]

2017

• Swarup Bhunia, An Chen, Ozgur Sinanoglu, and Jason M Fung, “Guest Editors’ Introduction: Security of Beyond-CMOS Devices: Issues and Opportunities”. Journal of Hardware and Systems (TETC), August 2017.
  [Article]
• Swarup Bhunia and Mark Tehranipoor, “Editorial for the Inaugural Issue of Journal of Hardware and Systems Security (HaSS)”. Journal of Hardware and Systems (HaSS), June 2017.
  [Article]

2016

• Domenic Forte, Ron Perez, Yongdae Kim, and Swarup Bhunia, “Guest Editors’ Introduction: Supply Chain Security for Cyber-Infrastructure”. IEEE Computer Magazine, 2016.
  [Article]

2015

• Swarup Bhunia, Jongsun Park, and Sandip Ray, “Guest Editors’ Introduction: Wearables, Implants, and Internet of Things (First Issue)”. IEEE Transactions on Multi-Scale Computing Systems (TMSCS), December 2015.
  [Article]
• Ramesh Karri, Farinaz Koushanfar, Ozgur Sinanoglu, Yiorgos Makris, Ken Mai, Ahmad Reza Sadeghi, and Swarup Bhunia, “Guest Editorial: Special Section on Hardware Security and Trust”. IEEE Transactions on CAD of Integrated Circuits and Systems (TCAD), June 2015.
  [Article]
• Saibal Mukhopadhyay, Kaushik Roy, Hillery Hunter, and Swarup Bhunia, “Guest Editorial: Computing in Emerging Technologies (Second Issue)”. IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), March 2015.
  [Article]
• Swarup Bhunia, Steve Majerus and Mohamad Sawan, “Introduction” in Implantable Biomedical Microsystems: Design Principles and Applications, Elsevier Science and Technology, MA, USA, 1st Edition, ISBN: 0323262082, February 2015.
  [Article]

2014

• Saibal Mukhopadhyay, Kaushik Roy, Hillery Hunter, and Swarup Bhunia, “Guest Editorial: Computing in Emerging Technologies (First Issue)”. IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), December 2014.
  [Article]

2013

• Swarup Bhunia, Leyla Nazhandali, and Dakshi Agrawal, “Guest Editors’ Introduction: Trusted System with Untrusted Components: An Emerging Design Need”. IEEE Design & Test of Computers (D&T), April 2013.
  [Article]
• Somnath Paul and Swarup Bhunia, “Preface” in Computing with Memory for Energy-Efficient Robust Systems, Springer, New York, USA, ISBN: 1461477972, September 2013.
  [Article]

2012

• Swarup Bhunia and Darrin J. Young, “Introduction to Special Issue on Implantable Electronics”. ACM Journal on Emerging Technologies in Computing Systems (JETC), Vol. 8, No. 2, pp. 7.1-7.2, June 2012.
  [Article]

2010

• Swarup Bhunia and Rahul Rao, “Guest Editors’ Introduction: Managing Uncertainty through Postfabrication Calibration and Repair”. IEEE Design & Test of Computers (D&T), Vol. 27, No. 6, pp. 4-5, November 2010.
  [Article]
• Swarup Bhunia and Saibal Mukhopadhyay, “Preface” in Low-Power Variation Tolerant Design in Nanometer Silicon, Springer, New York, USA, 1st Edition, ISBN: 1441974172, November 2010.
  [Article]
• Swarup Bhunia, “A Special Issue on 23^rd IEEE International Conference on VLSI Design, Bangalore, India, 3-7 January 2010”. Journal of Low Power Electronics (JOLPE), Vol. 6, No. 3, pp. 375-375, October 2010.

2018

• VLSI Circuits and Systems Letter (VCAL), official periodical of IEEE Computer Society Technical Committee on VLSI (TCVLSI), “Feature Member” of the Issue, November 2018.
• Foreward in the book “Hardware Security in DSP/Multimedia” by Anirban Sengupta, June 2018.

2016

• Dagstuhl Seminar 16342 Report, “Foundations of Secure Scaling”, Edited by Lejla Batina, Swarup Bhunia, Patrick Schaumont, and Jean-Pierre Seifert, Dec 2016.

2014

• Swarup Bhunia, “What is Hardware Security?”, Vol. 44, No. 12, ACM/SIGDA E-Newsletter, December, 2014.