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Publications

In this page we list the refereed as well as non-refereed (invited full paper or abstract) generated by the researchers of the Nanoscape Lab. Note that the underlined authors are graduate/undergraduate students of the Nanoscape lab.

  • [SPECTRUM’20] Roozbeh Tabrizian and Swarup Bhunia, “The Hidden Authenticators”, IEEE Spectrum, June 2020.
  • [Nature MicroNano’20] Sushant Rassay, Mehrdad Ramezani, Sumaiya Shomaji, Swarup Bhunia, and Roozbeh Tabrizian, Clandestine nanoelectromechanical tags for identification and authentication, Nature Microsystems & Nanoengineering, volume 6, Article number: 103 (2020).
  • [SPECTRUM’19] Swarup Bhunia and Soumyajit Mandal, “Fighting Fake Medicine using Nuclear Quadrupole Spectroscopy”, IEEE Spectrum, Nov 2019.
  • [PIEEE’18] Sandip Ray, Mark M. Tehranipoor, Eric Peeters, and Swarup Bhunia, “System-on-Chip Platform Security Assurance: Architecture and Validation”, Proceedings of the IEEE (PIEEE), in Special Issue on Secure Cyber Physical Systems, 106, no. 1, pp. 21-37, 2018.
  • [SPECTRUM’17] Sandip Ray, Abhishek Basak, and Swarup Bhunia, “Patchable Internet of Things”, IEEE Spectrum, November 2017.
  • [SPECTRUM’17]  Mark Tehranipoor, Ujjwal Guin, and Swarup Bhunia, “Invasion of the Hardware Snatchers: Cloned Electronics Pollute the Market”, IEEE Spectrum, May 2017.
  • [PIEEE’15] Robert Karam, Ruchir Puri, Swaroop Ghosh, and Swarup Bhunia, “Emerging Trends in Design and Applications of Memory based Computing and Content Addressable Memories”, Proceedings of the IEEE (PIEEE), in Special Issue on Memories in the Future of Information Processing, vol. 103, no. 8, pp. 1311-1330, 2015.
  • [PIEEE’14] Swarup Bhunia, Michael Hsiao, Mainak Banga, and Seetharam Narasimhan, “Hardware Trojan Attacks: Threat Analysis and Countermeasures”, Proceedings of the IEEE (PIEEE), vol. 102, no. 8, pp. 1229-1247, 2014.
  • [SCIENCE’10] Te-Hao Lee, Swarup Bhunia, and Mehran Mehregany, “Electromechanical Computing at 500 °C with Silicon Carbide”, Science, Sept 10, 2010, vol. 329, no. 5997, pp. 1316-1318. doi: 1126/science.1192511

2025

  • [TCAS-I’25] Peyman Dehghanzadeh, Baibhab Chatterjee, Soumyajit Mandal, and Swarup Bhunia, DF-PUF: A Dual-Function Programmable Entropy Source for Secure Authentication and Memory Reuse in ASICs”, tlo appear in IEEE Transactions on Circuits and Systems I (TCAS-I).
  • [TVLSI’25] Atri Chatterjee, Habibur Rahaman, and Swarup Bhunia, “ASTRA: Automated Insertion of Distributed Entropy Sources for Robust Authentication”, to appear in IEEE Transactions on Very Large Scale Integration Systems (TVLSI).
  • [TCAD’25] Ovishake Sen, Chukwufumnanya Ogbogu, Peyman Deghanzadeh, Janardhan Rao Doppa, Swarup Bhunia, Partha Pratim Pande, and Baibhab Chatterjee, “Look-Up Table based Energy-Efficient Architecture for Neural Accelerators (LANA)”, to appear in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD).
  • [D&T’25] Aritra Dasgupta, Sudipta Paria, Christopher Sozio, and Swarup Bhunia, “LATTE: Library Attack for Evaluating Hardware IP Protections against Reverse Engineering”, to appear in IEEE Design & Test (D&T) Magazine.
  • [IoTJ’25] Rohan Reddy Kalavakonda, Peyman Dehghanzadeh, Junjun Huan, Soumyajit Mandal, and Swarup Bhunia, “Fusion Intelligence: A Paradigm for Merging Natural and Artificial Intelligence”, to appear in IEEE Internet of Things Journal (IoTJ).
  • [TCHES’25] Aritra Dasgupta, Sudipta Paria and Swarup Bhunia, “HIPR: Hardware IP Protection through Low-Overhead Fine-Grain Redaction”, Transactions on Cryptographic Hardware and Embedded Systems (TCHES), Volume 2025, Issue 3.
  • [TCAS-I’25] Peyman Deghanzadeh, Soumyajit Mandal, and Swarup Bhunia, “MBM PUF: A Multi-Bit Memory-Based Physical Unclonable Function”, to appear in IEEE Transactions on Circuits and Systems I (TCAS-I).
  • [TC’25] Peyman Deghanzadeh, Ovishake Sen, Baibhab Chatterjee, and Swarup Bhunia, “LUNA-CiM: A Programmable Compute-in-Memory Fabric for Neural Network Acceleration”, to appear in IEEE Transactions on Computers (TC).
  • [TBioCAS’25] Junjun Huan, Vida Pashaei, Steve J. A. Majerus, Swarup Bhunia, and Soumyajit Mandal, “A Wearable Dual-Mode Probe for Image-Guided Closed-Loop Ultrasound Neuromodulation”, IEEE Trans. Biomed. Circuits System (TBioCAS), 19(2): 357-373 (2025).
  • [TIFS’25] Tanzim Mahfuz, Swarup Bhunia, and Prabuddha Chakraborty, “X-DFS: Explainable Artificial Intelligence Guided Design-for-Security Solution Space Exploration”, IEEE Trans. Inf. Forensics Secur. (TIFS), 20: 753-766 (2025).

2024

  • [TAI’24] Prabuddha Chakraborty and Swarup Bhunia, “A Self-Aware Digital Memory Framework Powered by Artificial Intelligence”, IEEE Transactions on Artificial Intelligence (TAI), 5(7): 3579-3594 (2024).
  • [TODAES’24] Moshiur Rahman, Jim Geist, Daniel Xing, Yuntao Liu, Ankur Srivastava, Travis Meade, Yier Jin, and Swarup Bhunia: Security Evaluation of State Space Obfuscation of Hardware IP through a Red Team-Blue Team Practice. ACM Trans. Design Autom. Electr. Syst. (TODAES), 29(3): 50:1-50:18 (2024).
  • [TCAD’24] Shubhra Deb Paul, Aritra Dasgupta, Swarup Bhunia: FDPUF: Frequency-Domain PUF for Robust Authentication of Edge Devices. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (TCAD), 43(11): 3479-3490 (2024).
  • [ESL’24] Sudipta Paria, Aritra Dasgupta, and Swarup Bhunia: SPELL: An End-to-End Tool Flow for LLM-Guided Secure SoC Design for Embedded Systems. IEEE Embed. Syst. Lett. (ESL), 16(4): 365-368 (2024).
  • [D&T’24] Prabuddha Chakraborty, Jonathan Cruz, Rasheed Almawzan, Tanzim Mahfuz, and Swarup Bhunia: Learning Your Lock: Exploiting Structural Vulnerabilities in Logic Locking. IEEE Des. Test (D&T), 41(2): 7-14 (2024).
  • [CEM’24] Reiner N. Dizon-Paradis, Rohan Reddy Kalavakonda, Prabuddha Chakraborty, and Swarup Bhunia: Pasteables: A Flexible and Smart “Stick-and-Peel” Wearable Platform for Fitness and Athletics. IEEE Consumer Electron. Mag. (CEM), 13(6): 17-27 (2024).
  • [ACCESS’24] Kelsey L. Horace-Herron, Naren Vikram Raj Masna, Swarup Bhunia, Soumyajit Mandal, and Sandip Ray: Nuclear Quadrupole Resonance for Substance Detection. IEEE Access 12: 111709-111722 (2024).
  • [ACCESS’24] Junjun Huan, Shubhra Deb Paul, Soumyajit Mandal, and Swarup Bhunia: PRISTINE: An Emulation Platform for PCB-Level Hardware Trojans. IEEE Access 12: 49291-49305 (2024).
  • [D&T’24] Anupam Chattopadhyay, Shivam Bhasin, Tim Güneysu, and Swarup Bhunia: Quantum-Safe Internet of Things. IEEE Des. Test (D&T), 41(5): 36-45 (2024).
  • [TC’24] Rajat Sadhukhan, Sayandeep Saha, Sudipta Paria, Swarup Bhunia, and Debdeep Mukhopadhyay, “VALIANT: An EDA Flow for Side-Channel Leakage Evaluation and Tailored Protection”, IEEE Trans. Computers (TC), 73(2): 436-450, 2024.  [Top Picks in HES 2025 Nomination]
  • [TCAD’24] Moshiur Rahman and Swarup Bhunia, “Practical Implementation of Robust State-Space Obfuscation for Hardware IP Protection”, IEEE Trans. Very Large Scale Integr. Syst. (TCAD), 32(2): 333-346, 2024.
  • [TVLSI’24] Christopher Vega, Patanjali SLPSK, and Swarup Bhunia, “IOLock: An Input/Output Locking Scheme for Protection Against Reverse Engineering Attacks”, IEEE Trans. Very Large Scale Integr. Syst. (TVLSI), 32(2): 347-360, 2024.

2023

  • [TC’23] Patanjali SLPSK, Sandip Ray, Swarup Bhunia: TREEHOUSE: A Secure Asset Management Infrastructure for Protecting 3DIC Designs, IEEE Transactions on Computers (TC), 2023.
  • [JRTE’23] Christine Wusylko, Zhen Xu, Kara M Dawson, Pavlo D Antonenko, Do Hyong Koh, Minyoung Lee, Amber E Benedict, Swarup Bhunia: Using a comic book to engage students in a cryptology and a cybersecurity curriculum, Journal of Research on Technology in Education (JRTE), 2023.
  • [SREP’23] Kelsey Horace-Herron, Naren Vikram Raj Masna, Peyman Dehghanzadeh, Soumyajit Mandal, Swarup Bhunia: Non-invasive authentication of mail packages using nuclear quadrupole resonance spectroscopy, Nature Scientific Reports, 2023.
  • [TC’23] Shubhra Deb Paul, Swarup Bhunia: CurIAs: Current-Based IC Authentication by Exploiting Supply Current Variations. IEEE Trans. Computers (TC), 72(2): 466-479 (2023).
  • [TVLSI’23] Aritra Bhattacharyay, Shuo Yang, Jonathan Cruz, Prabuddha Chakraborty, Swarup Bhunia, Tamzidul Hoque: An Automated Framework for Board-Level Trojan Benchmarking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (TVLSI), 42(2): 397-410 (2023).

2022

  • [TC’22] Patanjali SLPSK, Abhishek Anil Nair, Chester Rebeiro, Swarup Bhunia: SIGNED: A Challenge-Response Scheme for Electronic Hardware Watermarking, IEEE Transactions on Computers (TC), 2022.
  • [ACCESS’22] Junjun Huan, Nicholas Olexa, Brett Hochman, Swarup Bhunia, Rashmi Jha, Soumyajit Mandal: Intrinsically Secure Non-Volatile Memory Using ReRAM Devices. IEEE Access 10: 104577-104588 (2022).
  • [ESL’22] Prabuddha Chakraborty, Jonathan Cruz, Christopher Posada, Sandip Ray, Swarup Bhunia: HASTE: Software Security Analysis for Timing Attacks on Clear Hardware Assumption. IEEE Embed. Syst. Lett. 14(2): 71-74 (2022).
  • [ESL’22] Prabuddha Chakraborty, Reiner N. Dizon-Paradis, Swarup Bhunia: ARTS: A Framework for AI-Rooted IoT System Design Automation. IEEE Embed. Syst. Lett. 14(3): 151-154 (2022).
  • [IoTJ’22] Shubhra Deb Paul, Fengchao Zhang, Patanjali SLPSK, Amit Ranjan Trivedi, Swarup Bhunia: RIHANN: Remote IoT Hardware Authentication with Intrinsic Identifiers. IEEE Internet Things J. 9(24): 24615-24627 (2022).
  • [NCAA’22] Prabuddha Chakraborty, Swarup Bhunia: BINGO: brain-inspired learning memory. Neural Comput. and Appl. 34(4): 3223-3247 (2022).
  • [TCAD’22] Abdulrahman Alaql, Saranyu Chattopadhyay, Prabuddha Chakraborty, Tamzidul Hoque, Swarup Bhunia: LeGO: A Learning-Guided Obfuscation Framework for Hardware IP Protection. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(4): 854-867 (2022).
  • [TVLSI’22] Shuo Yang, Tamzidul Hoque, Prabuddha Chakraborty, Swarup Bhunia: Golden-Free Hardware Trojan Detection Using Self-Referencing. IEEE Trans. Very Large Scale Integr. Syst. 30(3): 325-338 (2022).
  • [TVLSI’22] Atul Prasad Deb Nath, Kshitij Raj, Swarup Bhunia, Sandip Ray: SoCCom: Automated Synthesis of System-on-Chip Architectures. IEEE Trans. Very Large Scale Integr. Syst. 30(4): 449-462 (2022).
  • [TVLSI’22] Mahmudul Hasan, Jonathan Cruz, Prabuddha Chakraborty, Swarup Bhunia, Tamzidul Hoque: Trojan Resilient Computing in COTS Processors Under Zero Trust. IEEE Trans. Very Large Scale Integr. Syst. 30(10): 1412-1424 (2022).

2021

  • [ASEE’21] Shuo Yang, Subhra Deb Paul, and Swarup Bhunia, “Hands-on Learning of Hardware and Systems Security”, Advances in Engineering Education (ASEE), Vol. 9, No. 2, Spring 2021.
  • [CEM’21] Rohan Reddy Kalavakonda, Naren Vikram Raj Masna, Anamika Bhuniaroy, Soumyajit Mandal, Swarup Bhunia: A Smart Mask for Active Defense against Coronaviruses and Other Airborne Pathogens. IEEE Consumer Electron. Mag. 10(2): 72-79 (2021).
  • [IoTJ’21] Prabuddha Chakraborty, Jonathan Cruz, Swarup Bhunia: MAGIC: Machine-Learning-Guided Image Compression for Vision Applications in Internet of Things. IEEE Internet Things J. 8(9): 7303-7315 (2021).
  • [JETC’21] Shubhra Deb Paul, Swarup Bhunia: SILVerIn: Systematic Integrity Verification of Printed Circuit Board Using JTAG Infrastructure. ACM J. Emerg. Technol. Comput. Syst. 17(3): 44:1-44:28 (2021).
  • [TCAD’21] Wei Hu, Chip-Hong Chang, Anirban Sengupta, Swarup Bhunia, Ryan Kastner, Hai Li: An Overview of Hardware Security and Trust: Threats, Countermeasures, and Design Tools. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(6): 1010-1038 (2021).
  • [TIFS’21] Abdulrahman Alaql, Swarup Bhunia: SARO: Scalable Attack-Resistant Logic Locking. IEEE Trans. Inf. Forensics Secur. 16: 3724-3739 (2021).
  • [TIFS’21] Prabuddha Chakraborty, Jonathan Cruz, Abdulrahman Alaql, Swarup Bhunia: SAIL: Analyzing Structural Artifacts of Logic Locking Using Machine Learning. IEEE Trans. Inf. Forensics Secur. 16: 3828-3842 (2021).
  • [TODAES’21] Indrani Roy, Chester Rebeiro, Aritra Hazra, Swarup Bhunia: FaultDroid: An Algorithmic Approach for Fault-Induced Information Leakage Analysis. ACM Trans. Design Autom. Electr. Syst. 26(1): 2:1-2:27 (2021).
  • [TVLSI’21] Fengchao Zhang, Shubhra Deb Paul, Patanjali SLPSK, Amit Ranjan Trivedi, Swarup Bhunia: On Database-Free Authentication of Microelectronic Components. IEEE Trans. Very Large Scale Integr. Syst. 29(1): 149-161 (2021).
  • [TVLSI’21] Abdulrahman Alaql, Md Moshiur Rahman, Swarup Bhunia: SCOPE: Synthesis-Based Constant Propagation Attack on Logic Locking. IEEE Trans. Very Large Scale Integr. Syst. 29(8): 1529-1542 (2021).
  • [TCHES’21] Keerthi K, Indrani Roy, Chester Rebeiro, Aritra Hazra, and Swarup Bhunia, “FEDS: Comprehensive Fault AttackExploitability Detection for SoftwareImplementations of Block Ciphers”, IACR Transactions on Cryptographic Hardware and Embedded Systems (TCHES), 2021.

2020

  • [CEM’20] Tamzidul Hoque, Patanjali SLPSK, Swarup Bhunia, Trust Issues in Microelectronics: The Concerns and the Countermeasures. IEEE Consumer Electron. Mag. 9(6): 72-83 (2020).
  • [SPECTRUM’20] Roozbeh Tabrizian and Swarup Bhunia, “The Hidden Authenticators”, IEEE Spectrum, June 2020.
  • [Nature MicroNano’20] Sushant Rassay, Mehrdad Ramezani, Sumaiya Shomaji, Swarup Bhunia, and Roozbeh Tabrizian, Clandestine nanoelectromechanical tags for identification and authentication, Nature Microsystems & Nanoengineering, volume 6, Article number: 103 (2020).
  • [D&T’20] Tamzidul Hoque, Rajat Subhra Chakraborty, Swarup Bhunia, Hardware Obfuscation and Logic Locking: A Tutorial Introduction. IEEE Des. Test 37(3): 59-77 (2020).
  • [TCAD’20] Indrani Roy, Chester Rebeiro, Aritra Hazra, Swarup Bhunia: SAFARI: Automatic Synthesis of Fault-Attack Resistant Block Cipher Implementations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(4): 752-765 (2020).
  • [TIFS’20] Atul Prasad Debnath, Srivalli Boddupalli, Swarup Bhunia, and Sandip Ray, “Resilient System-on-Chip Designs with NoC Fabrics”, IEEE Transactions on Information Forensics & Security (TIFS).
  • [JMR’20] Xinyao Tang, Naren V.R. Masna, Swarup Bhunia, and Soumyajit Mandal, “Single-Shot Spatially-Localized NQR using Field-Dependent Relaxation Rates”, Journal of Magnetic Resonance (JMR).
  • [D&T’20] Tamzidul Hoque, Rajat Shubhra Chakraborty, and Swarup Bhunia, and Sandip Ray, “Hardware Obfuscation and Logic Locking: A Tutorial Introduction”,IEEE IEEE Design & Test (D&T).
  • [TVLSI’20] Ahish Shylendra, Priyesh Shukla, Saibal Mukhopadhyay, Swarup Bhunia, and Amit Ranjan Trivedi, “Low Power Unsupervised Anomaly Detection by Non-Parametric Modeling of Sensor Statistics”, IEEE Transactions on Very Large-Scale Integration Systems (TVLSI).
  • [CEM’20] Tamzidul Hoque, Patanjali SLPSK, and Swarup Bhunia, “Trust Issues in Microelectronics: The Concerns and the Countermeasures”, IEEE Consumer Electronics Magazine (CEM).

2019

  • [TODAES’19] Tamzidul Hoque, Kai Yang, Robert Karam, Shahin Tajik, Domenic Forte, Mark Tehranipoor, and Swarup Bhunia, “Hidden in Plaintext: An Obfuscation-based Countermeasure against FPGA Bitstream Tampering Attacks”, ACM Transactions on Design Automation of Electronic Systems (TODAES).
  • [SPECTRUM’19]  Swarup Bhunia and Soumyajit Mandal, “Fighting Fake Medicine using Nuclear Quadrupole Spectroscopy”, IEEE Spectrum, Nov 2019.
  • [TVLSI’19] Ahish Shylendra, Swarup Bhunia, and Amit Ranjan Trivedi, “An Intrinsic and Database-free Authentication by Exploiting Process Variation in Back-end Capacitors”, IEEE Transactions on Very Large-Scale Integration Systems (TVLSI), 2019.
  • [ACCESS’19] Naren Vikram Raj Masna, Cheng Chen, Soumyajit Mandal, and Swarup Bhunia, “Robust Authentication of Consumables with Extrinsic Tags and Chemical Fingerprinting”, IEEE Access, 2019.
  • [CEM’19] Sumaiya Shomaji, Parisa Dehghanzadeh, Alex Roman, Domenic Forte, Swarup Bhunia, and Soumyajit Mandal, “Early Detection of Cardiovascular Diseases Using Wearable Ultrasound Device”, IEEE Consumer Electronics Magazine (CEM).
  • [TCAD’19] Indrani Roy, Chester Rebeiro, Aritra Hazra, and Swarup Bhunia, “SAFARI: Automatic Synthesis of Fault-Attack Resistant Block Cipher Implementations”, IEEE Transactions on CAD of Integrated Circuits and Systems (TCAD).

2018

  • [IJFST’18] Naren Vikram Raj Masna, Cheng Chen, Soumyajit Mandal, and Swarup Bhunia, “Authentication of Dietary Supplements through Nuclear Quadrupole Resonance (NQR) Spectroscopy”, International Journal of Food Science and Technology (IJFST), 2018.
  • [CEM’18] Naren Vikram Raj Masna, Shubhra Deb Paul, Cheng Chen, Soumyajit Mandal, and Swarup Bhunia, “Eat, but Verify: Low-Cost Portable Devices for Food Safety Analysis”, IEEE Consumer Electronics Magazine (CEM). [Featured Cover Story] [Best Paper Award]
  • [TIFS’18] Yuanwen Huang, Swarup Bhunia, and Prabhat Mishra, “Scalable Test Generation for Trojan Detection using Side Channel Analysis”, IEEE Transactions on Information Forensics & Security (TIFS).
  • [HASS’18] Sarah Amir, Bicky Shakya, Xiaolin Xu, Yier Jin, Swarup Bhunia, Mark Tehranipoor, and Domenic Forte, “Development and Evaluation of Hardware Obfuscation Benchmarks”, Journal of Hardware and Systems Security (HaSS), Springer, 2018.
  • [TODAES’18] Kun Yang, Haoting Shen, Domenic Forte, Swarup Bhunia, and Mark Tehranipoor, “Hardware-Enabled Pharmaceutical Supply Chain Security”, ACM Transactions on Design Automation of Electronic Systems (TODAES), 23, no. 2, pp. 23:1-23:26, 2018.
  • [PIEEE’18] Sandip Ray, Mark M. Tehranipoor, Eric Peeters, and Swarup Bhunia, “System-on-Chip Platform Security Assurance: Architecture and Validation”, Proceedings of the IEEE (PIEEE), in Special Issue on Secure Cyber Physical Systems, 106, no. 1, pp. 21-37, 2018.

2017

  • [TBIOCAS’17] Robert Karam, Steve Majerus, Dennis Bourbou, Margot S. Damaser, and Swarup Bhunia, “Tunable and Lightweight On-chip Event Detection for Implantable Bladder Pressure Monitoring Devices”, IEEE Transactions on Biomedical Circuits and Systems (TBioCAS), 11, no. 6, pp. 1303-1312, 2017.
  • [SPECTRUM’17] Sandip Ray, Abhishek Basak, and Swarup Bhunia, “Patchable Internet of Things”, IEEE Spectrum, November 2017.
  • [SPECTRUM’17] Mark Tehranipoor, Ujjwal Guin, and Swarup Bhunia, “Invasion of the Hardware Snatchers: Cloned Electronics Pollute the Market”, IEEE Spectrum, May 2017.
  • [HASS’17] Anthony Bahadir Lopez, Korosh Vatanparvar, Atul Prasad Deb Nath, Shuo Yang, Swarup Bhunia, Mohammad Abdullah Al Faruque, “A Security Perspective on the Battery Systems of the Internet of Things”, Journal of Hardware and Systems Security (HASS), Springer, 2017. [Top published content in the Journal (one of 3), 2017, By Springer]
  • [JMR’17] Cheng Chen, Fengchao Zhang, Swarup Bhunia, and Soumyajit Mandal, “Broadband Quantitative NQR for Authentication of Vitamins and Dietary Supplements”, The Journal of Magnetic Resonance (JMR), 2017.
  • [JOLPE’17] Kai Yang, Robert Karam, Somnath Paul, and Swarup Bhunia, “Energy-Efficient Reconfigurable Hardware Accelerators for Data-Intensive Applications”, Journal of Low Power Electronics (JOLPE) Special Issue on Special Issue on “New and Future Trends in Low Power Electronics”.
  • [ESL’17] Greg Stitt, Robert Karam, Kai Yang, and Swarup Bhunia, “A Uniquified Virtualization Approach to Hardware Security”, Embedded Systems Letters (ESL), Vol. 9, No. 3, Sept 2017.
  • [HASS’17] Bicky Shakya, Hassan Salmani, Domenic Forte, Swarup Bhunia, and Mark Tehranipoor, “Benchmarking of Hardware Trojans and Maliciously Affected Circuits”, Journal of Hardware and Systems Security (HASS), Springer, 2017. [Top published content in the Journal (one of 3), 2017, By Springer]
  • [JETTA’17] Tamzidul Hoque, Seetharam Narasimhan, Xinmu Wang, Sanchita Mal-Sarkar, and Swarup Bhunia, “Golden-Free Hardware Trojan Detection with High Sensitivity Under Process Noise”, Journal of Electronic Testing: Theory and Applications (JETTA), Springer, Vol. 33, No. 1, pp 107–124, Feb 2017.
  • [TDSC’17] Ujjwal Guin, Swarup Bhunia, Domenic Forte, and Mark M. Tehranipoor, “SMA: A System-Level Mutual Authentication for Protecting Electronic Hardware and Firmware”, IEEE Transactions on Dependable and Secure Computing (TDSC), Special Issue on Emerging Embedded and Cyber Physical System Security Challenges and Innovations.
  • [TIFS’17] Abhishek Basak, Swarup Bhunia, Thomas Tkacik, and Sandip Ray, “Security Assurance for System-on-Chip Designs with Untrusted IPs”, IEEE Transactions on Information Forensics & Security (TIFS), 2017.
  • [JETC’17] Robert Karam, Somnath Paul, Ruchir Puri, and Swarup Bhunia, “Memory-Centric Reconfigurable Accelerator for Classification and Machine Learning Applications”, ACM Journal of Emerging Technologies in Computing Systems (JETC).
  • [D&T’17] Dongyeob Shin, Jangwon Park, Jongsun Park, Somnath Paul, and Swarup Bhunia, “Adaptive ECC for Tailored Protection of Nanoscale Memory”, IEEE Design & Test of Computers (D&T).
  • [TMSCS’17] Sanchita Mal-Sarkar, Robert Karam, Seetharam Narasimhan, Anandaroop Ghosh, Aswin Raghav Krishna, and Swarup Bhunia, “Design and Validation for FPGA Trust under Hardware Trojan Attacks”, IEEE Transactions on Multi-Scale Computing Systems (TMSCS) Special Issue on Hardware/Software Cross-Layer Technologies for Trustworthy and Secure Computing.
  • [TVLSI’17] Wenchao Qian, Chris Babecki, Robert Karam, Somnath Paul, and Swarup Bhunia, “ENFIRE: A Spatio-temporal Fine-grained Reconfigurable Hardware”, IEEE Transactions on VLSI Systems (TVLSI).
  • [TCAS-II’17] Wenchao Qian, Pai-Yu Chen, Ligang Gao, Swarup Bhunia, and Shimeng Yu, “Energy-Efficient Adaptive Computing with Multifunctional Memory”, IEEE Transactions on Circuit and Systems-II (TCAS-II).
  • [TODAES’17] Kan Xiao, Domenic Forte, Yier Jin, Ramesh Karri, Swarup Bhunia, Mark Tehranipoor, “Hardware Trojans: Lessons Learned after One Decade of Research”, ACM Transactions on Design Automation of Electronic Systems (TODAES). [ACM Computing Reviews Notable Computing Books and Articles 2016, Hardware Category] [ACM TODAES 2017 Best Paper Award]

2016

  • [TVLSI’16] Robert Karam, Ruchir Puri, and Swarup Bhunia, “Energy-Efficient Adaptive Hardware Accelerator for Text Mining Application Kernels”, IEEE Transactions on VLSI Systems (TVLSI).
  • [TMSCS’16] Sandip Ray, Jongsun Park, and Swarup Bhunia, “Wearables, Implants, and Internet of Things: Towards Unifying Technologies to Support Diverse Paradigms”, IEEE Transactions on Multi-Scale Computing Systems (TMSCS). [Perspective paper in the Special issue on Wearables, Implants, and Internet of Things]. [Featured paper in the April-June 2016 Issue]
  • [TCBB’16] Cheng Chen, Fengchao Zhang, Soumyajit Mandal, Swarup Bhunia, Jamie Barras, and Kaspar Althoefer, “Authentication of medicines using nuclear quadrupole resonance spectroscopy”, IEEE/ACM Transactions on Computational Biology and Bioinformatics (TCBB), Special Issue on Special Issue on Emerging Security Trends for Biomedical Computations, Devices, and Infrastructures.
  • [TVLSI’16] Yu Zheng, Abhishek Basak, Fengchao Zhang, and Swarup Bhunia, “DScanPUF: A Delay-based Physical Unclonable Function Built into Scan Chain”, IEEE Transactions on Very Large-Scale Integration Systems (TVLSI), 2016.

2015

  • [TC’15] Christopher Babecki, Wenchao Qian, Somnath Paul, Robert Karam, and Swarup Bhunia, “A Memory-Centric Reconfigurable Hardware Accelerator for Security Applications”, IEEE Transactions on Computers (TC).
  • [PIEEE’15] Robert Karam, Ruchir Puri, Swaroop Ghosh, and Swarup Bhunia, “Emerging Trends in Design and Applications of Memory based Computing and Content Addressable Memories”, Proceedings of the IEEE (PIEEE), in Special Issue on Memories in the Future of Information Processing, vol. 103, no. 8, pp. 1311-1330, 2015.
  • [TBME’15] Robert Karam, Dennis Bourbeau, Steve Majerus, Iryna Makovey, Howard B. Goldman, Margot S. Damaser, and Swarup Bhunia, “Real-Time Contraction Event Detection from Bladder Pressure Recordings for Effective Diagnosis and Treatment of Urinary Incontinence”, IEEE Transactions on Biomedical Engineering (TBME).
  • [TCAD’15] Abhishek Basak and Swarup Bhunia, “P-Val: Antifuse-based Package-level Defense against Counterfeit ICs”, IEEE Transactions on Computer-Aided Design of of Integrated Circuits and Systems (TCAD).
  • [TCAD’15] Yu Zheng, Shuo Yang, and Swarup Bhunia, “SeMIA: Self-Similarity based IC Integrity Analysis”, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD).
  • [SST’15] Wenbo Chen, Wenchao Lu, Branden Long, Yibo Li, David Gilmer, Gennadi Bersuker, Swarup Bhunia, and Rashmi Jha, “Switching Characteristics of W/Zr/HfO2/TiN ReRAM Devices for Multi-level Cell Non-Volatile Memory Applications”, Semiconductor Science and Technology, IOP Publishing, 2015.
  • [JEDS’15] Tina He, Fengchao Xhang, Swarup Bhunia, and Philip Feng, “Silicon Carbide (SiC) Nanoelectromechanical Antifuse for Ultralow-Power FPGA Interconnects”, IEEE Journal of the Electron Devices Society (JEDS).
  • [TCAS-II’15] Wen Yueh, Subho Chatterjee, Muneeb Zia, Swarup Bhunia, and Saibal Mukhopadhyay, “A Memory-Based Logic Block with Optimized-for-Read SRAM for Energy-efficient Reconfigurable Computing Fabric”, IEEE Transactions on Circuits and Systems II (TCAS-II), 2015.
  • [JETCAS’15] Kaushik Roy, Deliang Fan, Xuanyao Fong, Mrigank Sharad, Somnath Paul, Subho Chatterjee, Swarup Bhunia, and Saibal Mukhopadhyay, “Exploring Spin Transfer Torque Devices for Unconventional Computing”, IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), 2015. [Perspective paper in the Special issue on Computing in Emerging Technologies].
  • [D&T’15] Swaroop Ghosh, Abhishek Basak, and Swarup Bhunia, “How Secure Are Printed Circuit Boards Against Trojan Attacks?”, IEEE Design and Test of Computers (D&T) Magazine, vol. PP, no. 99, pp. 1, 2014. [pre-print available online] [Top 3 Most Popular Article, May 2015]

2014

  • [TC’14] Xinmu Wang, Yu Zheng, Abhishek Basak and Swarup Bhunia, “IIPS: Infrastructure IP for SoC Security”, IEEE Transactions on Computers (TC), vol. PP, no. 99, pp. 1, 2014. [pre-print available online]
  • [PIEEE’14] Swarup Bhunia, Michael Hsiao, Mainak Banga, and Seetharam Narasimhan, “Hardware Trojan Attacks: Threat Analysis and Countermeasures”, Proceedings of the IEEE (PIEEE), vol. 102, no. 8, pp. 1229-1247, 2014.
  • [TVLSI’14] Somnath Paul, Aswin Krishna, Wenchao Qian, Robert Karam, and Swarup Bhunia, “MAHA: An Energy-Efficient Malleable Hardware Accelerator for Data-Intensive Applications”, IEEE Transactions on Very Large-Scale Integration Systems (TVLSI), PP, no. 99, pp. 1, 2014. [pre-print available online]
  • [TVLSI’14] Yu Zheng, Xinmu Wang and Swarup Bhunia, “SACCI: Scan-based Characterization through Clock Phase Sweep for Counterfeit Chip Detection”, IEEE Transactions on Very Large-Scale Integration Systems (TVLSI), vol. PP, no. 99, pp. 1, 2014. [pre-print available online]
  • [TBIOCAS’14] Abhishek Basak and Swarup Bhunia, “Implantable Ultrasonic Imaging Assembly for Automated Monitoring of Internal Organs”, IEEE Transactions on Biomedical Circuits and Systems (TBioCAS), 8, no. 6, pp. 881-890, 2014.
  • [TCAS-II’14] Jongsun Park, Jangwon Park and Swarup Bhunia, “VL-ECC: Variable Data-Length Error Correction Code for Embedded Memory in DSP Applications”, IEEE Transactions on Circuits and Systems II (TCAS-II), 2014. 61, NO. 2, FEBRUARY 2014, pp. 120-124. doi: 10.1109/TCSII.2013.2291091
  • [TVLSI’14] Anandaroop Ghosh, Somnath Paul, Jongsun Park, and Swarup Bhunia, “Improving Energy Efficiency in FPGA through Judicious Mapping of Computation to Embedded Memory Blocks”, IEEE Transactions on Very Large-Scale Integration Systems (TVLSI), 2014. 22, No. 6, June 2014, pp. 1314 – 1327. doi: 10.1109/TVLSI.2013.2271696

2013

  • [TC’13] Seetharam Narasimhan, Dongdong Du, Rajat Subhra Chakraborty, Somnath Paul, Francis Wolff, Christos Papachristou, Kaushik Roy, and Swarup Bhunia, “Hardware Trojan Detection by Multiple-Parameter Side-Channel Analysis”, IEEE Transactions on Computers, 2013. 62, No. 11, 2013, pp. 2183 – 2195. doi: 10.1109/TC.2012.200
  • [D&T’13] Seetharam Narasimhan, Wen Yueh, Xinmu Wang, Saibal Mukhopadhyay, and Swarup Bhunia, “Improving IC Security against Trojan Attacks through Integration of Security Monitors”, IEEE Design & Test of Computers (D&T) Special Issue on Smart Silicon, 2013. Volume: 29, Issue: 5, 2012, pp. 37 – 46. doi: 10.1109/MDT.2012.2210183

2012

  • [D&T’12] Swarup Bhunia, Miron Abramovici, Dakshi Agarwal, Paul Bradley, Michael S. Hsiao, Jim Plusquellic, and Mohammad Tehranipoor, “Protection against Hardware Trojan Attacks: Towards a Comprehensive Solution”, IEEE Design & Test of Computers, 2012. Volume: 30,Issue: 3, 2013, pp. 6 – 17.   doi: 1109/MDT.2012.2196252 [Top 20 Most Popular Article, May 2015]
  • [TCAS-I’12] Seetharam Narasimhan, Keerthi Kunaparaju, Swarup Bhunia, “Healing of DSP Circuits under Power Bound Using Post-Silicon Operand Bitwidth Truncation”, IEEE Transactions on CAS I (TCAS-I), 2012. Volume: 59, Issue: 9, 2012, pp. 1932 – 1941. doi: 1109/TCSI.2011.2180447 

2011

  • [JETTA’11] Rajat Subhra Chakraborty and Swarup Bhunia, “Security Against Hardware Trojan Attacks Using Key-based Design Obfuscation”, Journal of Electronic Testing: Theory and Applications (JETTA), Vol. 27, Issue 6, Nov 2011. doi:1007/s10836-011-5255-2
  • [JETCAS’11] Somnath Paul, Subho Chatterjee, Saibal Mukhopadhyay and Swarup Bhunia, “Energy-Efficient Reconfigurable Computing Using a Circuit-Architecture-Software Co-Design Approach”, IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS) [Special issue on Advances in Design of Energy-Efficient Circuits and Systems], 1,No. 3, pp. 369-380, 2011. doi: 10.1109/JETCAS.2011.2165232 
  • [D&T’11] Seetharam Narasimhan, Rajat Subhra Chakraborty, and Swarup Bhunia, “Hardware IP Protection during Evaluation Using Embedded Sequential Trojan”, IEEE Design & Test of Computers, 2011. doi: 1109/MDT.2011.70 
  • [TVLSI’11] Somnath Paul, Saibal Mukhopadhyay and Swarup Bhunia, “A Variation-Aware Preferential Design Approach for Memory Based Reconfigurable Computing”, IEEE Transactions on Very Large-Scale Integration Systems (TVLSI), 2011. doi:1109/TVLSI.2013.2295538 
  • [TC’11] Somnath Paul, Fang Cai, Xinmiao Zhang, and Swarup Bhunia, “Reliability-Driven ECC Allocation for Multiple Bit Error Resilience in Processor Cache”, IEEE Transactions on Computers (TC) Special Issue on Dependable Computer Architecture, Feb 2011. Volume: 60, Issue: 1, 2011, pp. 20-34. doi: 1109/TC.2010.203
  • [TBIOCAS’11] Seetharam Narasimhan, Hillel Chiel and Swarup Bhunia, “Ultra Low-Power and Robust Digital Signal Processing Hardware for Implantable Neural Interface Microsystems”, IEEE Transactions on Biomedical Circuits and Systems (TBioCAS), April 2011. Volume: 5, Issue: 2,  2011, pp. 169 – 178, doi: 10.1109/TBCAS.2010.2076281  

2010

  • [SCIENCE’10] Te-Hao Lee, Swarup Bhunia, and Mehran Mehregany, “Electromechanical Computing at 500 °C with Silicon Carbide”, Science, Sept 10, 2010, vol. 329, no. 5997, pp. 1316-1318. doi: 1126/science.1192511
  • [TVLSI’10] Somnath Paul and Swarup Bhunia, “Dynamic Transfer of Computation to Processor Cache for Yield and Reliability Improvement”, IEEE Transactions on Very Large-Scale Integration Systems (TVLSI), Volume: 19,Issue: 8, 2011, pp. 1368-1379. doi: 10.1109/TVLSI.2010.2049389
  • [TNANO’10] Somnath Paul, Saibal Mukhopadhyay and Swarup Bhunia, “A Circuit and Architecture Co-design Approach for Hybrid CMOS-STTRAM non-volatile FPGA“, IEEE Transactions on Nanotechnology (TNANO), 2010. Volume: 10, Issue: 3, 2011, Page(s): 385 – 394. doi: 10.1109/TNANO.2010.2041555
  • [TNANO’10] Somnath Paul and Swarup Bhunia, “A Scalable Memory-Based Reconfigurable Computing Framework for Nanoscale Crossbar”, IEEE Transactions on Nanotechnology (TNANO), 2010. Volume: 11, Issue: 3, 2012, Page(s): 451 – 462. doi: 10.1109/TNANO.2010.2041556 
  • [TODAES’10] Somnath Paul, Hamid Mahmoodi and Swarup Bhunia, “Low-Overhead Fmax Calibration at Multiple Operating Points Using Delay Sensitivity Based Path Selection,” ACM Transactions on Design Automation of Electronic Systems (TODAES), 15, no. 2, pp. 19.1:19.34, Feb 2010. doi: 10.1145/1698759.1698769

2009

  • [JETC’09] Rajat Subhra Chakraborty and Swarup Bhunia, “A Study of Asynchronous Design Methodology for Robust CMOS-Nano Hybrid System Design”, ACM Journal on Emerging Technologies in Computing Systems (JETC), vol. 5, no. 3, pp. 12:1-12:22, Aug 2009. doi: 1145/1568485.1568486
  • [TCAD’09] Rajat Subhra Chakraborty and Swarup Bhunia, “HARPOON: An Obfuscation based SoC Design Methodology for Hardware Protection,” IEEE Trans. on Computer Aided Design of Integrated Circuits and Systems (TCAD), vol. 28, no. 10, pp. 1493-1502, 2009. doi: 1109/TCAD.2009.2028166
  • [IET’09] Rajat Subhra Chakraborty, Somnath Paul, Yu Zhou, and Swarup Bhunia, “Low-Power Hybrid CMOS-NEMS FPGA: Circuit Level Analysis and Defect-Aware Mapping,” IET Computers and Digital Techniques (IET-CDT), vol. 3, no. 6, pp. 609-624, 2009. doi:1049/iet-cdt.2008.0135 
  • [TVLSI’09] Patrick Ndai, Nauman Rafique, Mithuna Thottethodi, Swaroop Ghosh, Swarup Bhunia, and Kaushik Roy, “Trifecta: A Non-Speculative Scheme to Exploit Common, Data-Dependent Subcritical Paths,” IEEE Trans. on Very Large-Scale Integration Systems (TVLSI), vol. 18, no. 1, pp. 53-65, 2009. DOI:1109/TVLSI.2008.2007491 

2008

  • [TC’08] Patrick Ndai, Swarup Bhunia, Amit Agarwal, and Kaushik Roy, “Within-Die Variation-Aware Scheduling in Superscalar Processors for Improved Throughput”, IEEE Transactions on Computers, vol. 57, no. 7, pp. 940-951, 2008. DOI:1109/TC.2008.40 
  • [JETTA’08] Swarup Bhunia, Hamid Mahmoodi, Arijit Raychowdhury, and Kaushik Roy, “Arbitrary Two-Pattern Delay Testing Using A Low-Overhead Supply Gating Technique”, Journal of Electronic Testing: Theory and Applications (JETTA), 24, no. 6, pp. 577-590, 2008. doi: 10.1007/s10836-008-5072-4
  • [TVLSI’08] Animesh Datta, Swarup Bhunia, Jung Hwan Choi, Saibal Mukhopadhyay, and Kaushik Roy “Profit Aware Circuit Design under Process Variations Considering Speed Binning”, IEEE Transactions on Very Large-Scale Integration Systems, 16, no. 7, pp. 806-815, 2008. doi: 10.1109/TVLSI.2008.2000364

2007

  • [TCAS-I’07] Rajat Subhra Chakraborty, Seetharam Narasimhan, and Swarup Bhunia, “Hybridization of CMOS with CNT-Based Nano Electromechanical Switch for Low Leakage and Robust Circuit Design”, IEEE Transactions on Circuits and Systems I (TCAS I), 54, no. 11, pp. 2480-2488, 2007. doi: 10.1109/TCSI.2007.907828 
  • [TODAES’07] Swaroop Ghosh, Swarup Bhunia, and Kaushik Roy, “Low-Power and Testable Circuit Synthesis Using Shannon Decomposition Based Structural Transformation”, ACM Transactions on Design Automation of Electronic Systems (TODAES), 12, no. 4, pp. 47:1-47:6, 2007. doi: 10.1145/1278349.1278360
  • [TVLSI’07] Amit Agarwal, Kunhyuk Kang, Swarup Bhunia, James Gallagher, and Kaushik Roy, “Device-Aware Yield-Centric Dual-Vt Design under Parameter Variations in Nano-Scale Technologies”, IEEE Transactions on Very Large-Scale Integration Systems, 15, no. 6, pp. 660-671, 2007. doi: 10.1109/TVLSI.2007.898683
  • [TCAD’07] Swaroop Ghosh, Swarup Bhunia, and Kaushik Roy, “CRISTA: A New Paradigm for Low-power, Variation-Tolerant and Adaptive Circuit Synthesis Using Critical Path Isolation”, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, vol. 26, no. 11, pp. 1947-1956, 2007 [Top 10 downloaded papers in Nov. 2007]. doi: 1109/TCAD.2007.896305 

2006

  • [TVLSI’06] Nilanjan Banerjee, Arijit Raychowdhury, Kaushik Roy, Swarup Bhunia, and Hamid Mahmoodi, “Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis”, IEEE Transactions on Very Large-Scale Integration Systems, vol. 14, no. 9, pp. 1034-1039, 2006. DOI:1109/ICCD.2005.80 
  • [TCAD’06] Swaroop Ghosh, Swarup Bhunia, Arijit Raychowdhury, and Kaushik Roy, “A Novel Delay Fault Testing Methodology Using Low Overhead Built-In Delay Sensor”, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, 25, no. 12, pp. 2934-2943, 2006. DOI:10.1109/TCAD.2006.882523 
  • [TCAD’06] Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, and Kaushik Roy, “Delay Modeling and Statistical Design of Pipelined Circuit under Process Variation”, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), vol. 25, no. 11, pp. 2427-2436, 2006. DOI:1109/TCAD.2006.873886 
  • [TCAD’06] Saibal Mukhopadhyay, Swarup Bhunia, and Kaushik Roy, “Modeling and Analysis of Loading Effect on Leakage of Nanoscaled Bulk-CMOS Logic Circuits”, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), 25, no. 8, pp. 1486-1495, 2006. DOI:10.1109/TCAD.2005.855934 

2005

  • [TVLSI’05] Arijit Raychowdhury, Bipul Paul, Swarup Bhunia, and Kaushik Roy, “Computing with Sub-threshold Leakage: Device/Circuit/Architecture Co-design for Ultralow-power Subthreshold Operation”, IEEE Transactions on Very Large-Scale Integration Systems (TVLSI), 13, no. 11, pp. 1213-1224, 2005. DOI:10.1109/TVLSI.2005.859590 
  • [TC’05] Swarup Bhunia, Animesh Datta, Nilanjan Banerjee, and Kaushik Roy, “GAARP: A Power-Aware GALS Architecture for Real-Time Algorithm-Specific Tasks”, IEEE Transactions on Computers (TC), 54, no. 6, pp. 752-766, 2005. DOI:10.1109/TC.2005.99 
  • [TVLSI’05] Qikai Chen, Hamid Mahmoodi, Swarup Bhunia, and Kaushik Roy, “Efficient testing of SRAM with optimized March sequences and a Novel DFT Technique for emerging failures due to process variations”, IEEE Transactions on Very Large-Scale Integration Systems (TVLSI), 13, no. 11, pp. 1286-1295, 2005. DOI:10.1109/TVLSI.2005.859565 
  • [TVLSI’05] Swarup Bhunia and Kaushik Roy, “A novel wavelet transform-based transient current analysis for fault detection and localization”, IEEE Transactions on Very Large-Scale Integration Systems (TVLSI), vol. 13, no. 4, pp. 503-507, 2005. DOI:1109/TVLSI.2004.842880 
  • [TVLSI’05] Swarup Bhunia, Hamid Mahmoodi, Saibal Mukhopadhyay, Debjyoti Ghosh, and Kaushik Roy, “Low-Power Scan Design Using First Level Supply Gating”, IEEE Transactions on Very Large-Scale Integration Systems (TVLSI), 13, no. 3, pp. 384-395, 2005. DOI:10.1109/TVLSI.2004.842885 
  • [JETTA’05] Swarup Bhunia, Arijit Roychowdhury, and Kaushik Roy, “Frequency Specification Testing of Analog Filters Using Wavelet Transform of Dynamic Supply Current”, Journal of Electronic Testing: Theory and Applications (JETTA), vol. 21, no. 3, pp. 243-255, 2005. DOI:1109/ISQED.2004.1283705 
  • [TECS’05] Lih-yih Chiou, Swarup Bhunia, and Kaushik Roy, “Synthesis of Application-Specific Highly Efficient Multi-Mode Cores for Embedded Systems”, ACM transactions on Embedded Computing System (TECS), 4, no. 1, pp. 168-188, 2005. DOI:10.1109/ISQED.2004.1283705 
  • [JETTA’05] Swarup Bhunia, Arijit Raychowdhury, and Kaushik Roy, “Defect Oriented Testing of Analog Circuits Using Wavelet Analysis of Dynamic Supply Current”, Journal of Electronic Testing: Theory and Applications (JETTA), vol. 21, no. 2, pp. 147-159, 2005. DOI: 1007/s10836-005-6144-3

2004

  • [TVLSI’04] Hai Li, Swarup Bhunia, Yiran Chen, Kaushik Roy, and T. N. Vijaykumar, “DCG: Deterministic Clock-Gating for Low-Power Microprocessor Design”, IEEE Transactions on Very Large-Scale Integration Systems (TVLSI), vol. 12, no. 3, pp. 245-254, 2004. DOI:1109/TVLSI.2004.824307 

2026

  • [USENIX Security’26] Sanskar Amgain, Daniel Lobo, Atri Chatterjee, Swarup Bhunia, and Fnu Suya, “HAMLOCK: HArdware-Model LOgically Combined attack”, to appear in USENIX Security, 2026.
  • [DATE’26] Mahmudul Hasan, Sudipta Paria, Swarup Bhunia, and Tamzidul Hoque, “COVERT: Trojan Detection in COTS Hardware via Statistical Activation of Microarchitectural Events”, to appear in Design, Automation and Test in Europe Conference (DATE), 2026.
  • [ISQED’26] Atri Chatterjee, Sudipta Paria, Aritra Dasgupta, Habibur Rahaman, Baibhab Chatterjee and Swarup Bhunia, “CRISP: Platform-Agnostic Unified Reconfigurable Hardware Security Primitive”, to appear in The 27th International Symposium on Quality Electronic Design (ISQED), 2026.
  • [AERA’26] Andrea Ramirez-Salgado, Lauren Eutsler, Anany Sharma, Woorin Hwang, Yessy E. Ambarwati, Talar Terzian, Megan Barnes, Nicole Dominguez, Dillon Donihue, Swarup Bhunia, Tamzidul Hoque, and Pasha Antonenko, “Engaging teenagers in community-centered edge AI projects,” to appear in the American Educational Research Association (AERA) annual meeting, Los Angeles, CA, USA, 2026
  • [AERA’26] Lauren Eutsler, Megan Barnes, Andrea Ramirez-Salgado, Yessy E. Ambarwati, Woorin Hwang, Talar Terzian, Anany Sharma, Tamzidul Hoque, Swarup Bhunia, and Pasha Antonenko, “Listening to Teachers: Adapting a Microelectronics and AI Curriculum Through Participatory Design,” to appear in the American Educational Research Association (AERA) annual meeting, Los Angeles, CA, USA, 2026.

2025

  • [ICCD’25] Sudipta Paria, Aritra Dasgupta, Dinesh R. Ankireddy, Prabuddha Chakraborty, and Swarup Bhunia, “LLM-assisted Scalable Formal Verification”, to appear in 2025 IEEE International Conference on Computer Design (ICCD), 2025. [In Special Session, GenAI Meets Silicon: LLMs in Hardware Design, Verification, and Security]
  • [NeurIPS Education’25] Andrea Ramirez-Salgado, Pasha Antonenko, Swarup Bhunia, Lauren Eutsler, Tamzidul Hoque, “Reimagining AI Education: Local, Tangible, and Personally Meaningful”, to appear in NeurIPS 2025 Education Program, San Diego, CA, USA, 2025.
  • [SmartIoT’25] Ankan Ghosh, Sumaiya Afroz Mila, Zongwei Zhen, Cong Chen, Swarup Bhunia, Sandip Ray, “A Machine Learning Approach for Real-time Gait Analysis”, to appear in The 9th IEEE International Conference on Smart Internet of Things (SmartIoT), 2025. [Best Paper Runner-up Award]
  • [ASEE ACE’25] Andrea Ramirez-Salgado, Pavlo Antonenko, Swarup Bhunia, Christine Wusylko, Woorin Hwang, Yessy Eka Ambarwati, “Voices of Hope: A Phenomenological Study on Women’s Self-Efficacy in Computer Engineering”, ASEE Annual Conference & Exposition, 2025.
  • [MLCAD’25] Dinesh R. Ankireddy, Sudipta Paria, Aritra Dasgupta, Sandip Ray, Swarup Bhunia, “LASSO: LLM-Aided Security Property Generation for Assertion-based SoC Verification”,  7th ACM/IEEE International Symposium on Machine Learning for CAD (MLCAD), 2025. [Best Paper Nomination]
  • [ICCAD’25] Raghul Saravanan, Sudipta Paria, Aritra Dasgupta, Swarup Bhunia, Sai Manoj Pudukotai Dinakarrao, “PROFUZZ: Directed Graybox Fuzzing via Module Selection and ATPG-Guided Seed Generation”, to appear in 2025 International Conference on Computer-Aided Design (ICCAD), 2025.
  • [ITC’25] Sudipta Paria, Md Rezoan Ferdous, Aritra Dasgupta, Atri Chatterjee, Swarup Bhunia, “LITE: ATPG-Aware Lightweight Scan Instrumentation for Enhancing Test Efficiency”, International Test Conference (ITC), 2025.
  • [MWSCAS’25] Junjun Huan, Jacob Pena, Zongwei Zhen, Swarup Bhunia, and Somyajit Manda, “A Wearable Ultrasound Device for Scapular Movement Tracking”, IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), 2025.
  • [DAC’25] Tanzim Mahfuz, Sudipta Paria, Tasneem Farhana Suha, Swarup Bhunia, and Prabuddha Chakraborty, “POLARIS: Explainable Artificial Intelligence for Mitigating Power Side-Channel Leakage”, 62nd Design Automation Conference (DAC), 2025.
  • [VTS’25] Dinesh Reddy Ankireddy, Sudipta Paria, Aritra Dasgupta, Sandip Ray, and Swarup Bhunia, “CLIP: A Structural Approach to Cut Points Matching for Logic Equivalence Checking”, 43rd IEEE VLSI Test Symposium (VTS), 2025.
  • [VTS’25] Tanzim Mahfuz, Pravin Gaikwad, Swarup Bhunia, and Prabuddha Chakraborty, “SALTY: Explainable Artificial Intelligence Guided Structural Analysis for Hardware Trojan Detection”, 43rd IEEE VLSI Test Symposium (VTS), 2025.
  • [VTS’25] Sudipta Paria, Aritra Dasgupta, and Swarup Bhunia, “Towards Automated Verification of IP and COTS: Leveraging LLMs in Pre- and Post-Silicon Stages”, 43rd IEEE VLSI Test Symposium (VTS), 2025. [In Special Session 5, AI-Driven Hardware Assurance: LLM Applications in VLSI Testing and Security]
  • [AERA’25] Andrea Ramirez-Salgado, Pasha Antonenko, Maya Israel, Kara M. Dawson, and Swarup Bhunia, “Advancing Transcendental Phenomenology as a Methodology for Exploring the Needs and Voices of Underrepresented Groups”, American Educational Research Association (AERA) Annual Meeting, 2025.

2024

  • [HOST’24] Sudipta Paria, Aritra Dasgupta, and Swarup Bhunia, “DiSPEL: A Framework for SoC Security Policy Synthesis and Distributed Enforcement”, IEEE HOST conference, 2024.
  • [ATS’24] Habibur Rahaman, Atri Chatterjee, and Swarup Bhunia, “SAMURAI: Safeguarding against Malicious Usage and Resilience of AI”, IEEE Asian Test Symposium (ATS), 2024.
  • [ATS’24] Sudipta Paria, Aritra Dasgupta, and Swarup Bhunia.” LATENT: Leveraging Automated Test Pattern Generation for Hardware Trojan Detection”, IEEE Asian Test Symposium (ATS), 2024. [Best Paper Nomination]
  • [ATS’24] Habibur Rahaman and Swarup Bhuinia, “Secure AI Systems: Emerging Threats and Defense Mechanisms”, IEEE Asian Test Symposium (ATS), 2024.
  • [PAINE’24] Moshiur Rahaman, Rasheed Almawzan, Aritra Dasgupta, Sudipta Paria and Swarup Bhuinia, “United We Protect: Protecting IP Confidentiality with Integrated Transformation and Redaction”, IEEE Physical Assurance and Inspection of Electronics (PAINE), 2024.
  • [ISVLSI’24] Reiner N. Dizon-Paradis, Aritra Dasgupta, Rohan Reddy Kalavakonda, Swarup Bhunia: Pasteables: A Flexible, Stick-and-Peel Smart Sensing Platform for Edge Applications. ISVLSI 2024: 539-543.
  • [ISVLSI’24] Rasheed Almawzan, Sudipta Paria, Aritra Dasgupta, Kostas Amberiadis, Swarup Bhunia: IP Security in Structured ASIC: Challenges and Prospects. ISVLSI 2024: 397-402.
  • [ISVLSI’24] Aritra Dasgupta, Sudipta Paria, Prabuddha Chakraborty, Swarup Bhunia: Splitting the Secrets: A Cooperative Trust Model for System-on-Chip Designs with Untrusted IPs. ISVLSI 2024: 325-330.
  • [ISVLSI’24] Prabuddha Chakraborty, Swarup Bhunia: An Intelligent Memory Framework for Resource Constrained IoT Systems. ISVLSI 2024: 296-299.
  • [ISQED’24] Kshitij Raj, Aritra Bhattacharyay, Swarup Bhunia, Sandip Ray: Trimming the Fat: A Minimum-Security Architecture for Protecting SoC Designs Against Supply Chain Threats. ISQED 2024.
  • [GLSVLSI’24] Rasheed Almawzan, Atri Chatterjee, Aritra Dasgupta, Swarup Bhunia: LISA: A Multi-Layered Iterative Framework for Hardening Obfuscation with Modular Unit Transformations. ACM Great Lakes Symposium on VLSI 2024: 588-591.
  • [GLSVLSI’24] Sudipta Paria, Aritra Dasgupta, Swarup Bhunia: Navigating SoC Security Landscape on LLM-Guided Paths. ACM Great Lakes Symposium on VLSI 2024: 252-257.
  • [BIOCAS’24] Deepanshu Trivedi, Junjun Huan, Arjuna Madanayake, Swarup Bhunia, Soumyajit Mandal: Compressed Plane-Wave Compounding for Efficient Imaging on Portable Ultrasound Devices. BioCAS 2024: 1-5.

2023

  • [SOCC’23] Prabuddha Chakraborty, Tasneem Suha, Swarup Bhunia, “Hardware Specification Aware Timing Side Channel Security Analysis”, SOCC 2023: 1-6.
  • [IJCNN’23] Krishnendu Guha, Amit Ranjan Trivedi, Swarup Bhunia, “Energy Efficient Memory-based Inference of LSTM by Exploiting FPGA Overlay”, IJCNN 2023: 1-7.

2022

  • [AICAS’22] Ahish Shylendra, Priyesh Shukla, Swarup Bhunia, Amit Ranjan Trivedi: Analog-Domain Time-Series Moment Extraction for Low Power Predictive Maintenance Analytics. AICAS 2022: 9-12.
  • [ASIANHOST’22] Jonathan Cruz, Pravin Gaikwad, Swarup Bhunia, “Analysis of Hardware Trojan Resilience Enabled through Logic Locking”, AsianHOST 2022: 1-6.
  • [ASIANHOST’22] Jonathan Cruz, Pravin Gaikwad, Abhishek Nair, Prabuddha Chakraborty, Swarup Bhunia: A Machine Learning Based Automatic Hardware Trojan Attack Space Exploration and Benchmarking Framework. AsianHOST 2022: 1-6.
  • [ASPDAC’22] Lakshmy, Chester Rebeiro, Swarup Bhunia: FORTIFY: Analytical Pre-Silicon Side-Channel Characterization of Digital Designs. ASP-DAC 2022: 660-665.
  • [DAC’22] Aritra Bhattacharyay, Prabuddha Chakraborty, Jonathan Cruz, Swarup Bhunia: VIPR-PCB: a machine learning based golden-free PCB assurance framework. DAC 2022: 793-798.
  • [ICCAD’22] Swarup Bhunia, Amitabh Das, Saverio Fazzari, Vivian Kammler, David Kehlet, Jeyavijayan Rajendran, Ankur Srivastava: Hardware IP Protection against Confidentiality Attacks and Evolving Role of CAD Tool. ICCAD 2022: 25.
  • [ITC’22] Prabuddha Chakraborty, Swarup Bhunia: AI-Driven Assurance of Hardware IP against Reverse Engineering Attacks. ITC 2022: 627-636.
  • [SMARTIOT’22] Reiner N. Dizon-Paradis, Oliver Ferrigno, Ishamor Reid, Swarup Bhunia: Light Pollution Monitoring Using a Modular IoT Sensor Platform. SmartIoT 2022: 28-35.
  • [VLSID’22] Abdulrahman Alaql, Aritra Dasgupta, Md Moshiur Rahman, Swarup Bhunia: SEVA: Structural Analysis based Security Evaluation of Sequential Locking. VLSID 2022: 126-131.

2021

  • [AsianHOST’21] Kshitij Raj, Arrush Hegde, Atul Prasad Deb Nath, Swarup Bhunia, Sandip Ray: SSEL: An Extensible Specification Language for SoC Security. AsianHOST 2021: 1-6.
  • [DATE’21] Sandip Ray, Atul Prasad Deb Nath, Kshitij Raj, Swarup Bhunia: CASTLE: Architecting Assured System-on-Chip Firmware Integrity. DATE 2021: 1781-1786.
  • [GLSVLSI’21] Sandip Ray, Atul Prasad Deb Nath, Kshitij Raj, Swarup Bhunia: The Curious Case of Trusted IC Provisioning in Untrusted Testing Facilities. ACM Great Lakes Symposium on VLSI 2021: 207-212.
  • [ISQED’21] Shuo Yang, Prabuddha Chakraborty, Patanjali SLPSK, Swarup Bhunia: Trusted Electronic Systems with Untrusted COTS. ISQED 2021: 198-203.
  • [ISQED’21] Abdulrahman Alaql, Xinmu Wang, Md Moshiur Rahman, Swarup Bhunia: SOMA: Security Evaluation of Obfuscation Methods via Attack Sequencing. ISQED 2021: 381-386.
  • [MWSCAS’21] Naren Vikram Raj Masna, Rohan Reddy Kalavakonda, Reiner Dizon, Swarup Bhunia: Smart and Connected Mask for Protection beyond the Pandemic. MWSCAS 2021: 676-679.

2020

  • [VTC’20] Prabuddha Chakraborty, Robert C Parker, Jonathan Cruz, Tamzidul Hoque, and Swarup Bhunia, “P2C2: Peer-to-Peer Car Charging”, IEEE 91st Vehicular Technology Conference (VTC), in Antwerp, Belgium, May 25-28, 2020.
  • [DATE’20] Milind Srivastava, Patanjali SLPSK, Indrani Roy, Chester Rebeiro, Aritra Hazra, Swarup Bhunia, SOLOMON: An Automated Framework for Detecting Fault Attack Vulnerabilities in Hardware. DATE 2020: 310-313.
  • [GLSVLSI’20] Tamzidul Hoque, Patanjali SLPSK, Swarup Bhunia, Trust Issues in COTS: The Challenges and Emerging Solution. ACM Great Lakes Symposium on VLSI 2020: 211-216.
  • [ISQED’20] Ahish Shylendra, Priyesh Shukla, Swarup Bhunia, and Amit Ranjan Trivedi, “Fault Attack Detection in AES by Monitoring Power Side-Channel Statistics”, International Symposium on Quality Electronic Design (ISQED), 2020.
  • [DATE’20] Milind Srivastava, PATANJALI SLPSK, Indrani Roy, Chester Rebeiro, Aritra Hazra, and Swarup Bhunia, “SOLOMON: An Automated Framework for Detecting Fault Attack Vulnerabilities in Hardware”, to appear in Design Automation and Test in Europe Conference (DATE), Grenoble, France, March 2020.

2019

  • [ASIANHOST’19] Abdulrahman Alaql, Domenic Forte, and Swarup Bhunia, “Sweep to the Secret: A Constant Propagation Attack on Logic Locking”, AsianHOST, 2019.
  • [ICCAD’19] Jungmin Park, JP Park, Swarup Bhunia, Alex Cho, and Mark Tehranipoor, “SCR-QRNG: Side-Channel Resistant Design using Quantum Random Number Generator”, International Conference on Computer Aided Design (ICCAD), 2019.
  • [NAECON’19] Nicholas Olexa, Swarup Bhunia, Soumyajit Mandal, and Rashmi Jha, “ReRAM-Based Intrinsically Secure Memory: A Feasibility Analysis”, National Aerospcae and Electronics Conference (NAECON), 2019.
  • [HOST’19] Prabuddha Chakraborty, Jonathan Cruz, and Swarup Bhunia, “SURF: Joint Structural Functional Attack on Logic Locking”, 12th IEEE Hardware Oriented Security and Trust (HOST), 2019.
  • [VTS’19] Abdulrahman Alaql, Tamzidul Hoque, Domenic Forte, Swarup Bhunia, “Quality Obfuscation for Reliable and Adaptive Hardware IP Protection”, 37th IEEE VLSI Test Symposium (VTS’19), Monterey, CA, USA, April 2019.

2018

  • [ASIANHOST’18] Prabuddha Chakraborty, Jonathan Cruz, and Swarup Bhunia, “SAIL: Machine Learning Guided Structural Analysis Attack on Hardware Obfuscation”, Asian Hardware Oriented Security and Trust Symposium (AsianHOST), Hong Kong, Dec. 17 – 18, 2018.
  • [ITC’18] Tamzidul Hoque, Jonathan Cruz, Prabuddha Chakraborty, and Swarup Bhunia, “Hardware IP Trust Validation: Learn (the Untrustworthy), and Verify”, 49th International Test Conference (ITC), Phoenix, AZ, USA, Oct. 26 – Nov. 1, 2018.
  • [ISTFA’18] Haoting Shen, Mark Tehranipoor, and Swarup Bhunia, “Tampering, Snooping, and Electromagnetic Attack Proof Coating on Printed Circuit Boards”, 44th International Symposium for Testing and Failure Analysis (ISTFA), Phoenix, AZ, USA, Oct. 26 – Nov. 1, 2018.
  • [ISLPED’18] Ahish Shylendra, Swarup Bhunia, and Amit Ranjan Trivedi, “Intrinsic and Database-free Watermarking in ICs by Exploiting Process and Design Dependent Variability in Metal-Oxide-Metal Capacitances”, ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), 2018.
  • [ISVLSI’18] Atul Prasad Debnath, Swarup Bhunia, and Sandip Ray, “ArtiFact: Architecture and CAD Flow for Efficient Formal Verification of SoC Security Policies”, IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Hong Kong SAR, China, July 9-11, 2018.
  • [ISVLSI’18] Kai Yang, Jungmin Park, Mark Tehranipoor, and Swarup Bhunia, “Robust Timing Attack Countermeasure on Virtual Hardware”, IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Hong Kong SAR, China, July 9-11, 2018.
  • [HILTON-HEAD’18] Mehrdad Ramezani, Angela Newsome, Swarup Bhunia, and Roozbeh Tabrizian, “A Nanomechanical Identification Tag Technology for Traceability and Authentication Applications”, Hilton Head 2018 Solid-State Sensors, Actuators & Microsystems Workshop, 2018.
  • [HOST’18] Kai Yang, Jungmin Park, Mark Tehranipoor, and Swarup Bhunia, “Hardware Virtualization for Protection against Power Analysis Attack”, 11th IEEE Hardware Oriented Security and Trust (HOST), 2018.
  • [VTS’18] Tamzidul Hoque, Xinmu Wang, Abhishek Basak, Robert Karam, and Swarup Bhunia, “Hardware Trojan Attack in Embedded Memory”, IEEE VLSI Test Symposium (VTS), 2018.
  • [NEMS’18] Angela Newsome, Mehrdad Ramezani, Mayur Ghatge, Fengchao Zhang, Swarup Bhunia, and Roozbeh Tabrizian, “Multi-Mode Micromechanical Resonant Tags for Traceability and Authentication Applications”, The 13th Annual IEEE Conference on Nano/Micro Engineered and Molecular Systems (NEMS), 2018.
  • [DATE’18] Jonathan Cruz, Yuanwen Huang, Prabhat Mishra, and Swarup Bhunia, “An Automated Configurable Trojan Insertion Framework for Dynamic Trust Benchmarks”, Design Automation and Test in Europe (DATE) Conference, 2018.
  • [ASPDAC’18] Sandip Ray, Atul Prasad Deb Nath, Abhishek Basak, and Swarup Bhunia, “System-on-Chip Security Architecture and CAD Framework for Hardware Patch”, 23rd Asia and South Pacific Design Automation Conference (ASPDAC), Korea, January 22-25, 2018.

2017

  • [BIOCAS’17] Fengchao Zhang, Naren Masna, Cheng Chen, Soumyajit Mandal, and Swarup Bhunia, “Authentication and Traceability of Food Products Through the Supply Chain Using NQR Spectroscopy”, IEEE BioCAS, FoodCAS Lecture session, Italy, October 2017.
  • [ASIANHOST’17] Robert Karam, Tamzidul Hoque, Kevin Butler, and Swarup Bhunia, “Mixed-Granular Architectural Diversity for Device Security in the Internet of Things”, AsianHOST, 2017.
  • [MWSCAS’17] Jungmin Park, Massimiliano Corba, Antonio E. de la Serna, Richard L. Vigeant, Mark Tehranipoor, and Swarup Bhunia, “ATAVE: a Framework for Automatic Timing Attack Vulnerability Evaluation”, IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS), 2017.
  • [MWSCAS’17] Kai Yang, Robert Karam, and Swarup Bhunia, “Interleaved Logic-in-Memory Architecture for Energy-Efficient Fine-Grained Data Processing”, IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS), 2017.
  • [MWSCAS’17] Tonmoy Dhar, Swarup Bhunia, and Amit Trivedi, “A solitary protection measure against scan chain, fault injection, and power analysis attacks on AES”, IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS), 2017.
  • [ASPDAC’17] Gustavo K. Contreras, Adib Nahiyan, Swarup Bhunia, Domenic Forte, Mark Tehranipoor, “Security Vulnerability Analysis of Design-for-Test Exploits for Asset Protection in SoCs,” 22nd Asia and South Pacific Design Automation Conference (ASPDAC), Tokyo, Japan, January 16-19, 2017.
  • [ASPDAC’17] Robert Karam, Tamzidul Hoque, Sandip Ray, Mark Tehranipoor, and Swarup Bhunia, “MUTARCH: Architectural Diversity for FPGA Device and IP Security,” 22nd Asia and South Pacific Design Automation Conference (ASPDAC), Tokyo, Japan, January 16-19, 2017.

2016

  • [CCS’16] Yuanwen Huang, Swarup Bhunia, and Prabhat Mishra, “MERS: Statistical Test Generation for Side-Channel Analysis based Trojan Detection”, ACM Conference on Computer and Communications Security (CCS), Vienna, Austria, October 24 – 28, 2016.
  • [RECONFIG’16] Robert Karam, Tamzidul Hoque, Sandip Ray, Mark Tehranipoor and Swarup Bhunia, “Robust Bitstream Protection in FPGA-based Systems through Low-Overhead Obfuscation”, International Conference on Reconfigurable Computing and FPGAs (ReConFig 2016), Cancun, Mexico, November 30 – December 2, 2016.
  • [BIOCAS’16] Robert Karam, Steve Majerus, Dennis Bourbeau, Margot Damaser, and Swarup Bhunia, “Ultralow-Power Data Compression for Implantable Bladder Pressure Monitor: Algorithm and Hardware Implementation”, IEEE Biomedical Circuits & Systems Conference (BIOCAS), 2016.
  • [HI-POCT’16] Sumaiya Shomaji, Abhishek Basak, Soumyajit Mandal, Swarup Bhunia, “A Wearable Carotid Ultrasound Assembly for Early Detection of Cardiovascular Diseases”, IEEE-NIH Special Topics Conference on Healthcare Innovations and Point-of-Care Technologies (HI-POCT), Cancun, Mexico, Nov 9-11, 2016.
  • [ISTFA’16] Zimu Guo, Bicky Shakya, Haoting Shen, Swarup Bhunia, Navid Asadizanjani, Domenic Forte, Mark Tehranipoor, “A New Methodology to Protect PCBs from Non-destructive Reverse Engineering”, International Symposium for Testing and Failure Analysis (ISTFA), Nov 6-10, Texas, USA, 2016.
  • [ICCAD’16] Dylan Ismari, Charles Lamech, Swarup Bhunia, Fareena Saqib, and James Plusquellic, “On Detecting Delay Anomalies Introduced by Hardware Trojans”, 35th IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2016.
  • [EMBC’16] Robert Karam, Swarup Bhunia, Steve Majerus, Steven Brose, Margot S. Damaser, Dennis Bourbeau, “Real-time, Autonomous Bladder Event Classification and Closed-Loop Control from Single-Channel Pressure Data”, 38th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), 2016.
  • [EMBC’16] Sumaiya Shomaji, Abhishek Basak, Soumyajit Mandal, Swarup Bhunia, “A Wearable Carotid Ultrasound Assembly for Early Detection of Cardiovascular Diseases”, 38th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), 2016. [Poster]
  • [DAC’16] Abhishek Basak, Swarup Bhunia, and Sandip Ray, “Exploiting Design-for-Debug for Flexible SoC Security Architecture”, Design Automation Conference (DAC), 2016.
  • [ISQED’16] Steven Paley, Tamzidul Hoque, and Swarup Bhunia, “Active Protection against PCB Physical Tampering”, 17th International Symposium on Quality Electronic Design (ISQED), 2016.
  • [DATE’16] Fengchao Zhang, James Plusquellic, and Swarup Bhunia, “Current based PUF Exploiting Random Variations in SRAM Cells”, Design Automation and Test in Europe (DATE),
  • [FPGA’16] Wenchao Qian, Christopher Babecki, Robert Karam, and Swarup Bhunia, “ENFIRE: An Energy-efficient Fine-grained Spatio-temporal Reconfigurable Computing Fabric”, 24th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), [Accepted as a poster presentation], 2016.
  • [ASPDAC’16] Andrew Hennessy, Yu Zheng, and Swarup Bhunia, “JTAG-Based Robust PCB Authentication for Protection against Counterfeiting Attacks”, 21st Asia and South Pacific Design Automation Conference (ASP-DAC), 2016.

2015

  • [ITC’15] Abhishek Basak, Fengchao Zhang, and Swarup Bhunia, “PiRA: IC Authentication Utilizing Intrinsic Variations in Pin Resistance”, International Test Conference (ITC), 2015.
  • [ICCAD’15] Abhishek Basak, Sandip Ray, and Swarup Bhunia, “A Flexible Architecture for Systematic Implementation of SoC Security Policies”, 34th IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2015.
  • [DAC’15] Jae-Won Jang, Jongsun Park, Swaroop Ghosh, and Swarup Bhunia, “Self-Correcting STTRAM under Magnetic Field Attacks”, Design Automation Conference (DAC), 2015.
  • [VTS’15] Andrew Hennessy, Fengchao Zhang, and Swarup Bhunia, “Trace Impedance based Authentication: A method towards Robust Counterfeit Printed Circuit Board (PCB) Detection”, 33rd IEEE VLSI Test Symposium (VTS), 2015.

2014

  • [DAC’14] Yu Zheng, Abhishek Basak, and Swarup Bhunia, “CACI: Dynamic Current Analysis towards Robust Recycled Chip Identification”, Design Automation Conference (DAC), 2014. DOI: 1145/2593069.2593102
  • [ICCAD’14] Wenjie Che, Swarup Bhunia and Jim Plusquellic, “A Non-Volatile Memory based Physically Unclonable Function without Helper Data”, IEEE International Conference on Computer Aided Design (ICCAD), 2014. ISBN: 978-1-4799-6277-8
  • [VTS’14] Abhishek Basak, Yu Zheng, and Swarup Bhunia, “Active Defense against Counterfeiting Attacks through Robust Antifuse-based On-Chip Locks”, 32nd IEEE VLSI Test Symposium (VTS), 2014. DOI: 1109/VTS.2014.6818793
  • [GLSVLSI’14] Wenchao Qian, Robert Karam, and Swarup Bhunia, “Trade-off between Energy and Quality of Service through Dynamic Operand Truncation and Fusion”, 24th GLSVLSI Symposium, 2014. DOI: 1145/2591513.2591561
  • [GLSVLSI’14] Sanchita Mal-Sarkar, Aswin Krishna, Anandaroop Ghosh and Swarup Bhunia, “Hardware Trojan Attacks in FPGA Devices: Threat Analysis and Effective Countermeasures”, 24th GLSVLSI Symposium, 2014. DOI: 1145/2591513.2591520
  • [NEMS’14] Vaishnavi Ranganathan, Srihari Rajgopal, Mehran Mehregany, and Swarup Bhunia, “Analysis of Practical Scaling Limits in Nanoelectromechanical Switches”, The 9th Annual IEEE International Conference on Nano/Micro Engineered and Molecular Systems (NEMS), 2014.

2013

  • [IEDM’13] Tina He, Vaishnavi Ranganathan, Rui Yang, Srihari Rajgopal, Mary Anne Tupta, Mehran Mehregany, Swarup Bhunia, and Philip X.-L. Feng, “Silicon Carbide (SiC) Nanoelectromechanical Switches and Logic Gates with Long Cycles and Robust Performance in Ambient Air and at High Temperature”, IEEE International Electron Devices Meeting (IEDM), 2013. doi: 1109/IEDM.2013.6724562
  • [NANOARCH’13] Hadi Hajimiri, Prabhat Mishra, Swarup Bhunia, Branden Long, Yibo Li, and Rashmi Jha, “Content-aware Encoding for Improving Energy Efficiency in Resistive Random Access Memory”, IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), 2013. DOI: 1109/NanoArch.2013.6623048
  • [NANOARCH’13] Vaishnavi Ranganathan, Tina He, Srihari Rajgopal, Mehran Mehregany, Philip X.-L. Feng, and Swarup Bhunia, “Robust Nanomechanical Non-Volatile Memory for Computing at Extreme”, 9th IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), 2013. DOI:1109/NanoArch.2013.6623042 
  • [DAC’13] Yu Zheng, MaryamSadat Hashemian, and Swarup Bhunia, “RESP: A Robust Physical Unclonable Function Retrofitted into Embedded SRAM Array”, Design Automation Conference (DAC), 2013.
  • [DAC’13] Xinmu Wang, Wen Yueh, Debapriya Basu Roy, Yu Zheng, Seetharam Narasimhan, Saibal Mukhopadhyay, Debdeep Mukhopadhyay, and Swarup Bhunia, “Role of Power Grid in Side Channel Attack and Power-Grid-Aware Secure Design”, Design Automation Conference (DAC), 2013.
  • [TRANSDUCERS’13] Tina He, Vaishnavi Ranganathan, Rui Yang, Srihari Rajgopal, Swarup Bhunia, Mehran Mehregany, and Philip X.-L. Feng, “Time-Domain AC Measurement of SiC Nanoelectromechanical Switches toward High Speed Operations”, 17th International Conference on Solid-State Sensors, Actuators and Microsystems (Transducers), 2013. DOI: 1109/Transducers.2013.6626855
  • [MRS’13] Yibo Li, Wenbo Chen, Ammaarah El-Amin, Rashmi Jha, Swarup Bhunia, and Philip X.-L. Feng, “A Reconfigurable Sensing and Computing Platform for Artificial Electronic Skins”, MRS Spring Meeting (Symposium TT: Materials and Processes for Artificial Skin), April 2013.
  • [NEMS’13] Tina He, Rui Yang, Srihari Rajgopal, Swarup Bhunia, Mehran Mehregany, and Philip X.-L. Feng, “Dual-gate silicon carbide (SiC) lateral nanoelectromechanical switches”, The 8th Annual IEEE International Conference on Nano/Micro Engineered and Molecular Systems (NEMS), 2013. [Best Student Paper Award] DOI: 1109/NEMS.2013.6559791 
  • [ASPDAC’13] Yu Zheng, Aswin Raghav Krishna, and Swarup Bhunia, “ScanPUF: Robust Ultralow Overhead PUF Using Scan Chain”, IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), 2013. DOI: 1109/ASPDAC.2013.6509668
  • [MEMS’13] Tina He, Rui Yang, Srihari Rajgopal, Mary Anne Tupta, Swarup Bhunia, Mehran Mehregany, and Philip X.-L. Feng, “Robust Silicon Carbide (SiC) Nanoelectromechanical Switches with Long Cycles in Ambient and High Temperature Conditions”, 26th IEEE International Conference on Micro Electro Mechanical Systems (MEMS), 2013. DOI:1109/MEMSYS.2013.6474292 
  • [POCHT’13] Abhishek Basak, Vaishnavi Ranganathan, and Swarup Bhunia, “A Wearable Ultrasonic Assembly for Point-Of-Care Autonomous Diagnostics of Malignant Growth”, IEEE EMBS Special Topic Conference on Point-of-Care Healthcare Technologies (PoCHT), 2013. [Student Paper Competition Winner (2nd Place)] DOI:1109/PHT.2013.6461301 
  • [VLSID’13] Maryamsadat Hashemian and Swarup Bhunia, “Ultralow-Power and Robust Embedded Memory for Bioimplantable Microsystems”, 26th IEEE International Conference on VLSI Design (VLSI-D), 2013. DOI:1109/VLSID.2013.164 
  • [VLSID’13] Hadi Hajimiri, Prabhat Mishra, and Swarup Bhunia, “Dynamic Cache Tuning for Efficient Memory Based Computing in Multicore Architectures”, 26th IEEE International Conference on VLSI Design (VLSI-D), 2013. DOI:1109/VLSID.2013.161 

2012

  • [DFTS’12] Xinmu Wang, Seetharam Narasimhan, Aswin Krishna, Tatini Mal-Sarkar, and Swarup Bhunia, “Software Exploitable Hardware Trojan Attacks in Embedded Processor”, IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS), 2012. [Special session on hardware security] [Student Paper Award] DOI:1109/DFT.2012.6378199 
  • [EMBC’12] Abhishek Basak, Vaishnavi Ranganathan, Seetharam Narasimhan, and Swarup Bhunia, “Implantable Ultrasonic Dual Functional Assembly Detection and Treatment of Anomalous Growth”, 34th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), 2012. [Student Best Paper Finalist] DOI:1109/EMBC.2012.6345898 
  • [GLSVLSI’12] Kamran Rahmani, Prabhat Mishra, and Swarup Bhunia, “RMBC: Reconfigurable Memory-based Computing for Performance and Energy Improvement in Multicore Architectures”, 22nd GLSVLSI Conference, 2012. DOI: 10.1145/2206781.2206851
  • [VLSID’12] Xinmu Wang, Seetharam Narasimhan, and Swarup Bhunia, “SCARE: Side-Channel Analysis based Reverse Engineering for Post-Silicon Validation”, 25th IEEE International Conference on VLSI Design (VLSI), 2012. DOI:1109/VLSID.2012.88 
  • [VLSID’12] Anandaroop Ghosh, Somnath Paul, and Swarup Bhunia, “Energy-Efficient Application Mapping in FPGA through Computation in Embedded Memory Blocks”, 25th IEEE International Conference on VLSI Design (VLSI), 2012. DOI:1109/VLSID.2012.108 
  • [VLSID’12] Lei Wang, Somnath Paul, and Swarup Bhunia, “Width-Aware Fine-Grained Dynamic Supply Gating: A Design Methodology for Low-Power Datapath and Memory”, 25th IEEE International Conference on VLSI Design (VLSI), 2012. [Best paper award] DOI:1109/VLSID.2012.94 

2011

  • [InfoSecHiComNet’11] Rajat Subhra Chakraborty, Seetharam Narasimhan and Swarup Bhunia, “Embedded Software Security through Key-based Control Flow Obfuscation”, International Conference on Security Aspects in Information Technology, High-Performance Computing and Networking (InfoSecHiComNet), 2011. DOI:1007/978-3-642-24586-2_5
  • [EMBC’11] Abhishek Basak, Seetharam Narasimhan, and Swarup Bhunia, “Low Power Implantable Ultrasound Imager for Online Monitoring of Tumor Growth”, 33rd Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), 2011. DOI:1109/IEMBS.2011.6090789 
  • [CHES’11] Aswin Raghav Krishna, Seetharam Narasimhan, Xinmu Wang, and Swarup Bhunia, “MECCA: A Robust Low-Overhead PUF using Embedded Memory Array”, Workshop on Cryptographic Hardware and Embedded Systems (CHES), 2011. [Best paper candidate – one of the top 13 papers considered for best paper award] DOI: 1007/978-3-642-23951-9_27
  • [NANOARCH’11] Xinmu Wang, Seetharam Narasimhan, Somnath Paul, and Swarup Bhunia, “NEMTronics: Symbiotic Integration of Nanoelectronic and Nanomechanical Devices for Energy-Efficient Adaptive Computing”, 7th IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), 2011. DOI:1109/NANOARCH.2011.5941506 
  • [HOST’11] Seetharam Narasimhan, Xinmu Wang, Dongdong Du, Rajat Subhra Chakraborty, and Swarup Bhunia, “TeSR: A Robust Temporal Self-Referencing Approach for Hardware Trojan Detection”, 4th IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), 2011. DOI:1109/HST.2011.5954999 
  • [HEALTHCOM’11] Abhishek Basak, Seetharam Narasimhan, and Swarup Bhunia, “KiMS: Kids’ Health Monitoring System at Day-Care Centers using Wearable Sensors and Vocabulary-based Acoustic Signal Processing”, 13th IEEE International Conference on e-Health Networking, Application & Services (Healthcom), 2011. DOI:1109/HEALTH.2011.6026744 
  • [NVMW’11] Subho Chatterjee, Saibal Mukhopadhyay, Mitchelle Rasquinha, Sudhakar Yalamanchili, Swarup Bhunia, and Somnath Paul, “Energy Efficient Circuit-System Codesign For Spin Torque Transfer Random Access Memory (STTRAM) In Submicron Technologies”, Non-Volatile Memories Workshop (NVMW), 2011.
  • [DATE’11] Xinmu Wang, Seetharam Narasimhan, Aswin Krishna, Francis G. Wolff, Hari and Swarup Bhunia, “High-Temperature (>500°C) FPGA Using SiC Nano-Electro-Mechanical System Switches”, Design Automation and Test in Europe (DATE), 2011. DOI: 1109/DATE.2011.5763175
  • [DATE’11] Subidh Ali, Debdeep Mukhopadhyay, Rajat Subhra Chakraborty, and Swarup Bhunia, “Multi-level Attack: An Emerging Threat Model for Cryptographic Hardware”, Design Automation and Test in Europe (DATE), 2011. DOI:1109/DATE.2011.5763307 
  • [FPGA’11] Somnath Paul and Swarup Bhunia, “Memory Based Computing: Reshaping the fine-grained logic in a reconfigurable framework”, 18th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), 2011. [Accepted as a poster presentation, ~25% acceptance rate] doi:1145/1950413.1950481
  • [VLSID’11] Keerthi Kunaparaju, Seetharam Narasimhan, and Swarup Bhunia, “VaROT: Variation-Tolerant DSP Circuits Using Post-Silicon Truncation of Operand Width”, IEEE International Conference on VLSI Design (VLSI), 2011. DOI: 1109/VLSID.2011.58

2010

  • [AHS’10] Seetharam Narasimhan, Somnath Paul, Rajat Subhra Chakraborty, Francis Wolff, Christos Papachristou, Daniel Weyer, and Swarup Bhunia, “System Level Self-Healing for Parametric Yield and Reliability Improvement under Power Bound,” NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 2010. DOI:1109/AHS.2010.5546231 
  • [CHES’10] Rajat Subhra Chakraborty and Swarup Bhunia, “Embedded Software Security Through Key-based Obfuscation”, Poster presentation in Workshop on Cryptographic Hardware and Embedded Systems (CHES), 2010.
  • [EMBC’10] Seetharam Narasimhan, Xinmu Wang, and Swarup Bhunia, “Implantable Electronics: Emerging Design Issues and An Ultra Light-weight Security Solution”, IEEE Engineering in Medicine and Biology Society Conference (EMBC), 2010. DOI: 1109/IEMBS.2010.5627327
  • [IGCC’10] Seetharam Narasimhan, David McIntyre, Yu Zhou, Francis Wolff, Daniel Weyer, and Swarup Bhunia, “A Supply-Demand Model Based Scalable Energy Management System for Improved Energy Utilization Efficiency”, IEEE International Green Computing Conference (IGCC), 2010. [Acceptance rate: 30% (22 out of 73)]. DOI:1109/GREENCOMP.2010.5598260 
  • [CHES’10] Dongdong Du, Seetharam Narasimhan, Rajat Subhra Chakraborty and Swarup Bhunia, “Self-Referencing: A Scalable Side-Channel Approach for Hardware Trojan Detection”, Workshop on Cryptographic Hardware and Embedded Systems (CHES), 2010, pp 173-187. DOI: 1007/978-3-642-15031-9_12
  • [ISLPED’10] Somnath Paul and Swarup Bhunia, “VAIL: Variation-Aware Issue Logic and Performance Binning for Processor Yield and Profit Improvement”, International Symposium on Low Power Electronics and Design (ISLPED), 2010.
  • [IOLTS’10] David McIntyre, Francis Wolff, Chris Papachristou, and Swarup Bhunia, “Trustworthy Computing in a Multi-Core System Using Distributed Scheduling”, IEEE International On-Line Testing Symposium (IOLTS), 2010, PP. 211-213. DOI:1109/IOLTS.2010.5560200 
  • [NAECON’10] Chris Papachristou, Swarup Bhunia, and Francis Wolff, “Network Calibration of Embedded Sensors”, IEEE National Aerospace and Electronics Conference (NAECON), 2010. DOI:1109/NAECON.2010.5712959 
  • [HOST’10] Dongdong Du, Seetharam Narasimhan, Rajat Subhra Chakraborty, Chris Papachristou, Somnath Paul, and Swarup Bhunia, “Multiple-Parameter Side-Channel Analysis: A Non-invasive Hardware Trojan Detection Approach”, IEEE Symposium on Hardware Oriented Security and Trust (HOST), 2010. [Best paper candidate] DOI:1109/HST.2010.5513122 
  • [VLSID’10] Rajat Subhra Chakraborty and Swarup Bhunia, “RTL Hardware IP Protection Using Key-Based Control and Data Flow Obfuscation”, 23rd International Conference on VLSI Design, pp. 405-410, 2010. DOI:1109/VLSI.Design.2010.54 

2009

  • [NANO’09] Somnath Paul, Subho Chatterjee, Saibal Mukhopadhyay and Swarup Bhunia, “Nanoscale Reconfigurable Computing Using Non-Volatile 2-D STTRAM Array”, 9th International Conference on Nanotechnology (IEEE Nano), pp. 880-883, 2009.
  • [ICCAD’09] Somnath Paul, Subho Chatterjee, Saibal Mukhopadhyay and Swarup Bhunia, “A Circuit-Software Co-Design Approach for Improving EDP in Reconfigurable Frameworks,” IEEE International Conference on Computer Aided Design (ICCAD), pp. 109-112, 2009. doi: 1145/1687399.1687423
  • [ICCAD’09] Somnath Paul, Saibal Mukhopadhyay and Swarup Bhunia, “A Variation-Aware Preferential Design Approach for Memory Based Reconfigurable Computing,” IEEE International Conference on Computer Aided Design (ICCAD), pp. 180-183, 2009. DOI:1109/TVLSI.2013.2295538 
  • [ICCAD’09] Rajat Subhra Chakraborty and Swarup Bhunia, “Security against Hardware Trojan through a Novel Application of Design Obfuscation,” IEEE International Conference on Computer Aided Design (ICCAD), pp. 113-116, 2009. doi: 1145/1687399.1687424
  • [HOST’09] Rajat Subhra Chakraborty and Swarup Bhunia, “Security through Obscurity: An Approach for Protecting Register Transfer Level Hardware IP,” IEEE Hardware Oriented Security and Trust (HOST) Workshop, pp. 96-99, 2009. DOI:1109/HST.2009.5224963 
  • [HOST’09] David McIntyre, Francis Wolff, Chris Papachristou, Swarup Bhunia and Dan Weyer, “Dynamic Evaluation of Hardware Trust,” IEEE Hardware Oriented Security and Trust (HOST) Workshop, pp. 108-111, 2009. DOI:1109/HST.2009.5224990 
  • [CHES’09] Rajat Subhra Chakraborty, Francis Wolff, Somnath Paul, Christos Papachristou and Swarup Bhunia, “MERO: A Statistical Approach for Hardware Trojan Detection,” Workshop on Cryptographic Hardware and Embedded Systems (CHES), pp. 396-410, 2009. [Acceptance rate: 20%]. doi: 1007/978-3-642-04138-9_28
  • [EMBC’09] Seetharam Narasimhan, Hillel J. Chiel and Swarup Bhunia, “A Preferential Design Approach for Energy-Efficient and Robust Implantable Neural Signal Processing”, IEEE Engineering in Medicine and Biology Society Conference (EMBC), pp. 6383-6386, 2009 [Student Best Paper Finalist]. doi: 1109/IEMBS.2009.5333729
  • [TRANSDUCERS’09] Te-Hao Lee, Kevin M. Speer, Xiaoan Fu, Swarup Bhunia, and Mehran Mehregany, “Polycrystalline Silicon Carbide NEMS for High-Temperature Logic,” pp. 900-903, Transducers, 2009. doi: 1109/SENSOR.2009.5285907

2008

  • [NMDC’08] Te-Hao Lee, Kevin M. Speer, Kenji Okino, Xiaoan Fu, Swarup Bhunia, and Mehran Mehregany, “Polycrystalline-SiC Nanoelectromechanical Switches for High-Temperature Switching and Logic Applications”, IEEE Nanotechnology and Device Conference (NMDC), 2008.
  • [ICCAD’08] Rajat Subhra Chakraborty and Swarup Bhunia, “Hardware Protection Through Netlist-Level Obfuscation”, IEEE International Conference on Computer Aided Design (ICCAD), pp. 674-677, 2008. DOI:1109/ICCAD.2008.4681649 
  • [ICCAD’08] Somnath Paul, Saibal Mukhopadhyay, and Swarup Bhunia, “Hybrid CMOS-STTRAM FPGA Design Optimization for Low Power and High Integration Density”, IEEE International Conference on Computer Aided Design (ICCAD), 589-592, 2008. DOI:10.1109/ICCAD.2008.4681636 
  • [EMBC’08] Seetharam Narasimhan, Miranda Cullins, Hillel Chiel, and Swarup Bhunia, “Wavelet-Based Neural Pattern Analyzer for Behaviorally Significant Burst Pattern Recognition”, IEEE Engineering in Medicine and Biology Society Conference (EMBC), pp. 38-41, 2008. DOI:1109/IEMBS.2008.4649085 
  • [HOST’08] Rajat Subhra Chakraborty, Somnath Paul, and Swarup Bhunia, “On-Demand Transparency for Improving Hardware Trojan Detectability”, IEEE Hardware Oriented Security and Trust (HOST) Workshop, pp. 48-50, 2008. DOI:1109/HST.2008.4559048 
  • [DAC’08] Seetharam Narasimhan, Somnath Paul, and Swarup Bhunia, “Collective Computing Based on Swarm Intelligence”, Design Automation Conference (DAC), pp. 349-350, 2008 [as a WACI (Wild and Crazy Ideas) paper]. doi: 1145/1391469.1391561
  • [NANOARCH’08] Somnath Paul and Swarup Bhunia, “Reconfigurable Computing Using Content Addressable Memory for Improved Performance and Resource Usage”, Design Automation Conference (DAC), pp. 786-791, 2008. doi: 1145/1391469.1391670
  • [ISQED’08] Rajat Subhra Chakraborty and Swarup Bhunia, “Micropipeline-Based Asynchronous Design Methodology for Robust System Design Using Nanoscale Crossbar”, IEEE International Symposium on Quality Electronic Design (ISQED), pp. 697-701, 2008. doi: 1109/ISQED.2008.4479822
  • [GLSVLSI’08] Matthew Holtz, Seetharam Narasimhan, and Swarup Bhunia, “On-die CMOS Voltage Droop Detection and Dynamic Compensation”, GLSVLSI, pp. 35-40, 2008. doi: 1145/1366110.1366122
  • [ISQED’08] Yu Zhou, Somnath Paul, and Swarup Bhunia, “Towards Uniform Temperature Distribution in SOI Circuits Using Carbon Nanotube Based Thermal Interconnect”, IEEE International Symposium on Quality Electronic Design (ISQED), pp. 861-866, 2008. doi: 1109/ISQED.2008.4479851
  • [DATE’08] Lawrence Leinweber and Swarup Bhunia, “Fine-Grained Supply Gating Through Hypergraph Partitioning and Shannon Decomposition for Active Power Reduction”, Design Automation and Test in Europe (DATE), pp. 373-378, 2008. doi: 1145/1403375.1403466
  • [DATE’08] Yu Zhou, Somnath Paul and Swarup Bhunia, “Harvesting Wasted Heat in a Microprocessor Using Thermo-Electric Generators: Modeling, Analysis and Measurement”, Design Automation and Test in Europe (DATE), pp. 98-103, 2008. doi: 1145/1403375.1403403
  • [DATE’08] Francis Wolff, Christos Papachristou, Rajat Subhra Chakraborty, and Swarup Bhunia, “Towards Trojan-Free Trusted ICs: Problem Analysis and a Low-Overhead Detection Scheme”, Design Automation and Test in Europe (DATE), pp. 1362-1365, 2008. doi: 1145/1403375.1403703
  • [VLSID’08] Rajat Subhra Chakraborty, Somnath Paul, and Swarup Bhunia, “Analysis and Robust Design of Diode-Resistor Based Nanoscale Crossbar PLA Circuits”, International Conference on VLSI Design, pp. 441-446, 2008. doi: 1109/VLSI.2008.44
  • [ASPDAC’08] Somnath Paul and Swarup Bhunia, “MBARC: A Scalable Memory Based Reconfigurable Computing Framework for Nanoscale Devices”, Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 77-82, 2008. DOI:1109/ASPDAC.2008.4484057 

2007

  • [BIOCAS’07] Seetharam Narasimhan, Yu Zhou, Hillel J. Chiel, and Swarup Bhunia, “Low-Power VLSI Architecture for Neural Data Compression Using Vocabulary-based Approach”, IEEE Biomedical Circuits and Systems Conference (BioCAS), 2007. DOI:1109/BIOCAS.2007.4463327 
  • [ICCD’07] Somnath Paul and Swarup Bhunia, “Memory Based Computation Using Embedded Cache for Processor Yield and Reliability Improvement”, International Conference on Computer Design (ICCD), 341-346, 2007. doi: 10.1109/ICCD.2007.4601922
  • [ICCAD’07] Somnath Paul, Siva Krishnamurthy, Hamid Mahmoodi, and Swarup Bhunia, “Low-Overhead Design Technique for Calibration of Maximum Frequency at Multiple Operating Points”, IEEE International Conference on Computer Aided Design (ICCAD), pp. 401-404, 2007. DOI:1109/ICCAD.2007.4397298 
  • [ISLPED’07] Yu Zhou, Shijo Thekkel, and Swarup Bhunia, “Low power FPGA Design Using Hybrid CMOS-NEMS Approach”, International Symposium on Low Power Electronics and Design (ISLPED), pp. 14-19, 2007. DOI:1145/1283780.1283785 
  • [IOLTS’07] Somnath Paul, Rajat Chakraborty, and Swarup Bhunia, “Defect-Aware Configurable Computing in Nano-crossbar Fabric for Improved Yield”, IEEE International On-Line Testing Symposium (IOLTS), 29-36, 2007. DOI:10.1109/IOLTS.2007.25 
  • [IOLTS’07] Swaroop Ghosh, Patrick N. Dai, Swarup Bhunia, and Kaushik Roy, “Tolerance to Small Delay Defects by Adaptive Clock Stretching”, IEEE International On-Line Testing Symposium (IOLTS), 244-252, 2007. DOI:10.1109/IOLTS.2007.67 
  • [EMBS’07] Seetharam Narasimhan, Massood Tabib-Azar, Hillel J. Chiel, and Swarup Bhunia, “Neural Data Compression with Wavelet Transform: A Vocabulary Based Approach”, IEEE EMBS Conference on Neural Engineering, pp. 666-669, 2007. DOI:1109/CNE.2007.369760 
  • [VTS’07] Somnath Paul, Rajat Subhra Chakraborty, and Swarup Bhunia, “VIm-Scan: A Low Overhead Scan Design Approach for Protection of Secret Key in Scan-Based Secure Chips”, IEEE VLSI Test Symposium (VTS), pp. 455-460, 2007. DOI:1109/VTS.2007.89 
  • [NANOTECH’07] Rajat Chakraborty, Seetharam Narasimhan, Swarup Bhunia, “Hybridization of CMOS with CNT-based Complementary Nano Electro-Mechanical Switch for Low-Leakage and Robust Embedded Memory Design”, Nanotech, pp. 134-137, 2007.
  • [ISQED’07] Siva Krishnamurthy, Somnath Paul, and Swarup Bhunia, “Adaptation to Temperature-Induced Delay Variations in Logic Circuits Using Low-Overhead Online Delay Calibration”, IEEE International Symposium on Quality Electronic Design (ISQED), 755-760, 2007. doi: 10.1109/ISQED.2007.29
  • [DATE’07] Swaroop Ghosh, Swarup Bhunia, and Kaushik Roy, “Low-Overhead Circuit Synthesis for Temperature Adaptation Using Dynamic Voltage Scheduling”, Design Automation and Test in Europe (DATE),1532-1537, 2007. DOI:10.1109/DATE.2007.364518 
  • [ASPDAC’07] Swarup Bhunia, Massood Tabib Azar, and Daniel Saab, “Ultralow-Power Reconfigurable Computing with Complementary Nano-Electromechanical Carbon Nanotube Switches”, Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 86-91, 2007. doi: 1109/ASPDAC.2007.357797

2006

  • [NANOARCH’06] Swarup Bhunia, Massood Tabib-Azar, and Daniel Saab, “Ultralow-Power Adaptive System Architecture Using Complementary Nano-Electromechanical Carbon Nanotube Switches,” NANOARCH, Boston, MA, 2006.
  • [SOC’06] Massood Tabib-Azar, Swarup Bhunia, and Daniel Saab, “Complimentary Nano-Electromechanical Carbon Nanotube Switches,” Soc. 602, 2138, Cancun, Mexico, 2006. doi:10.1149/1.2357277
  • [ICCAD’06] Swaroop Ghosh, Swarup Bhunia, and Kaushik Roy, “A New Paradigm for Low-power, Variation-Tolerant and Adaptive Circuit Synthesis Using Critical Path Isolation”, IEEE International Conference on Computer Aided Design (ICCAD), pp. 619-624, 2006. doi: 1145/1233501.1233628
  • [ASPDAC’06] Ashish Goel, Swarup Bhunia, Hamid Mahmoodi, and Kaushik Roy, “A Low-Overhead Design of Soft-Error-Tolerant Scan Flip-Flop with Enhanced-Scan Capability”, Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 665-670, 2006. doi: 1109/ASPDAC.2006.1594762
  • [ASPDAC’06] Animesh Datta, Swarup Bhunia, Jung Hwan Choi, Saibal Mukhopadhyay, and Kaushik Roy, “Speed Binning Aware Design Methodology to Improve Profit under Parameter Variations”, Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 712-717, 2006 [Best Paper Nomination]. DOI:1109/ASPDAC.2006.1594770 
  • [DATE’06] Nilanjan Banerjee, Swarup Bhunia, Hamid Mahmoodi, and Kaushik Roy, “Low Power Synthesis of Dynamic Logic Circuits Using Fine-Grained Clock Gating”, Design Automation and Test in Europe (DATE), pp. 862-867, 2006. DOI:1109/DATE.2006.243769 
  • [IOLTS’06] Swaroop Ghosh, Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy, “Delay Fault Localization in Test-Per-Scan BIST Using Built-In Delay Sensor”, pp. 31-36, International On-Line Test Symposium (IOLTS), 2006. DOI:1109/IOLTS.2006.19 
  • [DATE’06] Arijit Raychowdhury, Bipul Chandra Paul, Swarup Bhunia, Kaushik Roy, “Ultralow power computing with sub-threshold leakage: a comparative study of bulk and SOI technologies”, Design and Test in Europe (DATE), 2006, pp. 183. DOI:1109/DATE.2006.243768 

2005

  • [ISLPED’05] Amit Agarwal, Kunhyuk Kang, Swarup Bhunia, and Kaushik Roy, “Effectiveness of Low Power Dual-Vt Designs in Nano-Scale Technologies under Process Parameter Variations”, International Symposium on Low Power Electronics and Design (ISLPED), pp. 14-19, 2005. DOI:1109/LPE.2005.195478 
  • [DAC’05] Swarup Bhunia, Hamid Mahmoodi, Nilanjan Banerjee, Qikai Chen, and Kaushik Roy, “A Novel Synthesis Approach for Active Leakage Power Reduction Using Supply Gating”, Design Automation Conference (DAC), pp. 479-484, 2005. DOI:1109/DAC.2005.193857 
  • [VTS’05] Qikai Chen, Hamid Mahmoodi, Swarup Bhunia, and Kaushik Roy, “Analysis of New Fault Mechanisms and Test Methodologies for Failures in SRAM due to Process Variations”, VLSI Test Symposium (VTS), 2005. DOI:1109/TVLSI.2005.859565 
  • [IOLTS’05] Animesh Datta, Saibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy, “Yield Prediction of High Performance Pipelined Circuit with Respect to Delay Failures in Sub-100nm Technology”, International On-Line Test Symposium (IOLTS), 2005, pp. 275-280, Cited by 3. DOI:1109/IOLTS.2005.71 
  • [ATS’05] Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, Kaushik Roy, “A Statistical Approach to Area-Constrained Yield Enhancement for Pipelined Circuits under Parameter Variations”, Asian Test Symposium (ATS), 2005, pp. 170-175, Cited by 2. DOI: 1109/ATS.2005.16 
  • [ATS’05] Swaroop Ghosh, Swarup Bhunia, Kaushik Roy, “Shannon Expansion Based Supply-Gated Logic for Improved Power and Testability”, Asian Test Symposium (ATS), pp. 404-409, 2005. DOI:1109/ATS.2005.98 
  • [DATE’05] Swarup Bhunia, Hamid Mahmoodi-Meimand, Arijit Raychowdhury, Kaushik Roy, “A Novel Low-overhead Delay Testing Technique for Arbitrary Two-Pattern Test Application”, Design and Test in Europe (DATE), pp. 1136-1141, 2005. DOI:1109/DATE.2005.27 
  • [DATE’05] Saibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy, “Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits”, Design and Test in Europe (DATE), pp. 224-229, 2005. DOI: 1109/DATE.2005.210 
  • [ICCD’05] Nilanjan Banerjee, Arijit Raychowdhury, Swarup Bhunia, Hamid Mahmoodi-Meimand, Kaushik Roy, “Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis”, International Conference on Computer Design (ICCD), pp. 1034-1039, 2005. DOI:1109/ICCD.2005.80 
  • [ISQED’05] Animesh Datta, Swarup Bhunia, Nilanjan Banerjee, Kaushik Roy, “A Power-Aware GALS Architecture for Real-Time Algorithm-Specific Tasks”, International Symposium on Quality Electronic Design (ISQED), pp. 358-363, 2005. DOI:1109/ISQED.2005.12 
  • [ISQED’05] Swarup Bhunia, Hamid Mahmoodi-Meimand, Debjyoti Ghosh, Kaushik Roy, “Power Reduction in Test-Per-Scan BIST with Supply Gating and Efficient Scan Partitioning”, International Symposium on Quality Electronic Design (ISQED), pp. 453-458, 2005. DOI:1109/ISQED.2005.96 

2004

  • [HOST’04] Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy, “Frequency Specification Testing of Analog Filters Using Wavelet Transform of Dynamic Supply Current”, International Symposium on Quality Electronic Design (ISQED), pp. 243-255, 2004. DOI:1109/ISQED.2004.1283705 
  • [DFT’04] Swarup Bhunia, Hamid Mahmoodi-Meimand, Arijit Raychowdhury, Kaushik Roy, “First Level Hold: A Novel Low-Overhead Delay Fault Testing Technique”, IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT), pp. 314-315, 2004. DOI: 1109/DFTVS.2004.1347854 
  • [IOLTS’04] Debjyoti Ghosh, Swarup Bhunia, Kaushik Roy, “A Technique to Reduce Power and Test Application Time in BIST”, International On-Line Test Symposium (IOLTS), pp. 182-184, 2004. DOI:1109/OLT.2004.1319684 
  • [ICCD’04] Swarup Bhunia, Hamid Mahmoodi, Saibal Mukhopadhyay, Debjyoti Ghosh, and Kaushik Roy, “A Novel Low Power Scan Design Technique Using Supply Gating”, International Conference on Computer Design (ICCD), pp. 60-65, 2004.[Best Paper Award] DOI: 1109/ICCD.2004.1347900 
  • [DATE’04] Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy, “Trim Bit Setting of Analog Filters Using Wavelet-Based Supply Current Analysis”, Design Automation and Test in Europe (DATE), 2004, 10704-10709, 2004. DOI:10.1109/DATE.2004.1268941 

2003

  • [LATW’03] Swarup Bhunia and Kaushik Roy, “Defect Oriented Testing of Analog Circuits Using Wavelet Analysis of Dynamic Current”, Latin American Test Workshop (LATW), 2003. [Best Paper Award]
  • [DFT’03] Debjyoti Ghosh, Swarup Bhunia, and Kaushik Roy, “Multiple Scan Chain Design Technique for Power Reduction during Test Application in BIST”, IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT), pp. 191-196, 2003. DOI:1109/DFTVS.2003.1250112 
  • [HPCA’03] Hai Li, Swarup Bhunia, Yiran Chen, Kaushik Roy, and T. N. Vijaykumar. “Deterministic Clock Gating for Microprocessor Power Reduction”, International Symposium on High-Performance Computing Architecture (HPCA), 113-122, 2003. DOI:10.1109/HPCA.2003.1183529 
  • [DATE’03] Lih-yih Chiou, Swarup Bhunia, and Kaushik Roy, “Synthesis of Application Specific Multi-Mode Systems”, Design automation and Test in Europe (DATE), 96-101, 2003. DOI:10.1109/DATE.2003.1253593 

2002

  • [DATE’02] Swarup Bhunia and Kaushik Roy, “Fault Detection and Diagnosis Using Wavelet Based Transient Current Analysis”, Design Automation and Test in Europe (DATE), pp. 1118-1119, 2002. DOI:1109/DATE.2002.998474 
  • [VTS’02] Swarup Bhunia and Kaushik Roy, “Dynamic Supply Current Testing of Analog Circuits Using Wavelet Transform”, VLSI Test Symposium (VTS), 302-307, 2002. DOI:10.1109/VTS.2002.1011158 
  • [DAC’02] Swarup Bhunia, Kaushik Roy and Jaume Segura “A Novel Wavelet Transform Based Transient Current Analysis for Fault Detection and Localization”, Design Automation Conference (DAC), 361-366, 2002. DOI:10.1109/DAC.2002.1012650 
  • [ATS’02] Swarup Bhunia, Hai Li, and Kaushik Roy, “Gated-Ground Cache: A High Performance IDDQ-Testable Cache for Scaled CMOS Technologies”, IEEE Asian Test Symposium (ATS), pp. 157-162, 2002. DOI:1109/ATS.2002.1181704 

2000

  • [VLSID’00] Swarup Bhunia, Subhasish Majumdar, Ayon Sirkar, and Susmita Sur-kolay, “Topological Routing amidst Polygonal Obstacles”, 13th International VLSI Conference (VLSI Design), pp. 274-279, 2000. DOI:1109/ICVD.2000.812621 

1999

  • [VLSID’99] Swarup Bhunia, Soumya Ghosh, Pramod Kumar, Partha Das, and Jayanta Mukherjee, “Design, Simulation and Synthesis of an ASIC for Fractal Image Coding”, 12th International VLSI Conference (VLSI Design), pp. 544-549, 1999. DOI:1109/ICVD.1999.745211 

2026

  • [FPGA’26] Aritra Dasgupta, Jonathan Cruz, Peyman Deghanzadeh, Pravin Gaikwad, Sudipta Paria, and Swarup Bhunia, “PROM: Protection against Reverse Engineering Attacks through Programmable Logic Macros”,  34th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2026), February 22-24, 2026. [Abstract]
  • [ISQED’26] Habibur Rahaman, Sudipta Paria, and Swarup Bhunia, “Evolving Landscape of Attacks on AI Hardware and Robust Defenses”, to appear in Special Session on “Security for AI and AI for Security”, in the 27th International Symposium on Quality Electronic Design (ISQED), 2026.
  • [GOMACTECH’26] Mahmudul Hasan, Tamzidul Hoque, Sudipta Paria, and Swarup Bhunia, “A Statistical Approach to Detecting Trojans in COTS Hardware Using Microarchitectural Events”, GOMACTech Conference, New Orleans, LA, USA, March 9-12, 2026.
  • [GOMACTECH’26] Habibur Rahaman, Atri Chatterjee, and Swarup Bhunia, “SAMURAI: Runtime Attack Detection in AI Accelerators Using AI Performance Counters”, GOMACTech Conference, New Orleans, LA, USA, March 9-12, 2026.
  • [GOMACTECH’26] Raghul Saravanan, Sai Manoj Pudukotai Dinakarrao, Sudipta Paria, Aritra Dasgupta, and Swarup Bhunia, Intelligent Graybox Fuzzing via ATPG-Guided Seed Generation and Submodule Analysis”, GOMACTech Conference, New Orleans, LA, USA, March 9-12, 2026.
  • [GOMACTECH’26] Tambiara Tabassum, Dinesh Reddy Ankireddy, Sudipta Paria, Sandip Ray, and Swarup Bhunia, “A System-on-Chip Instrumentation Architecture for Efficient Post-Silicon Fuzzing”, GOMACTech Conference, New Orleans, LA, USA, March 9-12, 2026.
  • [GOMACTECH’26] Atri Chatterjee, Habibur Rahaman, and Swarup Bhunia, “ASTRA: Automated Insertion of Distributed Entropy Sources for Robust Authentication”, GOMACTech Conference, New Orleans, LA, USA, March 9-12, 2026.
  • [GOMACTECH’26] Tanzim Mahfuz, Tasneem Suha, Prabuddha Chakraborty, Sudipta Paria, and Swarup Bhunia, “XAI Enabled Power Side-Channel Estimation & Mitigation in Sensitive Digital Hardware”, GOMACTech Conference, New Orleans, LA, USA, March 9-12, 2026.

2025

  • [CODES+ISSS’25] Atri Chatterjee, Habibur Rahman, and Swarup Bhunia, “MARVEL-PUF: A Robust Multi-Bit Memory PUF for FPGA-based Embedded Systems Security”, to appear in Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), 2025. [Published in the Work-in-Progress Section]
  • [ASEE’25] Woorin Hwang, Andrea Ramirez-Salgado, Rohan Reddy Kalavakonda, Yessy Eka Ambarwati, Pavlo Antonenko, and Swarup Bhunia, “WIP: Empowering First-Year Engineering Students for Career Choices through Hands-On AI Hardware Experiences”, ASEE Annual Conference & Exposition, 2025.
  • [ASEE’25] Andrea Ramirez-Salgado, Swarup Bhunia, and Pavlo Antonenko, “Empowering Future Engineers: An Inclusive Curriculum for AIoT and Intelligent Embedded Systems”, 2025 ASEE Annual Conference & Exposition, Montreal, Canada, June 22-25, 2025.
  • [GOMACTECH’25] Sudipta Paria, Aritra Dasgupta, and Swarup Bhunia, “Post-Silicon Hardware Trojan Detection with High Confidence Leveraging Automated Test Patterns”, GOMACTech Conference, Pasadena, CA, USA, March 17-20, 2025.
  • [GOMACTECH’25] Emmanuel Elias, Tambiara Tabassum, Kshitij raj, Atri Chatterjee, Swarup Bhunia, and Sandip ray, “MCSE: A Low-Cost Security Engine for Protecting Edge Devices Against Supply-Chain Attacks”, GOMACTech Conference, Pasadena, CA, USA, March 17-20, 2025.
  • [GOMACTECH’25] Tanzim Mahfuz, Prabuddha Chakraborty, and Swarup Bhunia, “X-DFS: An Explainable Artificial Intelligence Guided Framework for Design-for-Security”, GOMACTech Conference, Pasadena, CA, USA, March 17-20, 2025.
  • [GOMACTECH’25] Aritra Dasgupta, Sudipta Paria, Swarup Bhunia, and Christopher Sozio, and Andrew Lukefahr, “Library-Attack: reverse Engineering Approach for Evaluating Hardware IP Protection”, GOMACTech Conference, Pasadena, CA, USA, March 17-20, 2025.

2024

  • [GOMACTECH’24] Andrea Ramirez-Salgado, Tanvir Hossain, Swarup Bhunia, Pavlo Antonenko, “Board 393: Supporting Hardware Engineering Career Choice in First-Year Engineering Students”, ASEE Conferences, 2024.
  • [GOMACTECH’24] Kshitij raj, Atri Chatterjee, Swarup Bhunia, and Sandip ray, “A Security engine Solution for Protecting SoC designs Against Supply-Chain Threats”, GOMACTech Conference, Charleston, SC, USA, May 18-21, 2024.
  • [GOMACTECH’24] Mahmudul Hasan, Tamzidul Hoque, Sudipta Paria and Swarup Bhunia, “A Statistical Approach to Detecting Trojans in COTS Hardware Using Microarchitectural Events”, GOMACTech Conference, Charleston, SC, USA, May 18-21, 2024.
  • [GOMACTECH’24] Christopher vega, Patanjali SlPSK, Ravalika Karnati, and Swarup Bhunia, “VARI-CHECK: Authentication of CoTS devices using ML-Based variability Characterization”, GOMACTech Conference, Charleston, SC, USA, May 18-21, 2024.
  • [GOMACTECH’24] Aritra Dasgupta, Jackson Fugate, Greg Stitt, Swarup Bhunia, Nij Dorairaj, and David Kehlet, “RIPPER: Low-overhead Fine-grain redaction Tool Flow for hardware IP Protection”, GOMACTech Conference, Charleston, SC, USA, May 18-21, 2024.

2023

  • [GOMACTECH’23] Maneesh Merugu, Md Moshiur Rahman, Aritra dasgupta, Swarup Bhunia, and Sandip Ray, “Formal equivalence checking for locked and Redacted Hardware designs”, GOMACTech Conference, San Diego, CA, USA, May 20-23, 2023.
  • [GOMACTECH’23] Christopher vega, Patanjali SLPSK, and Swarup Bhunia, “IOLock: An Input/Output Protection Scheme for Chip and PCB Protection”, GOMACTech Conference, San Diego, CA, USA, May 20-23, 2023.
  • [GOMACTECH’23] Aritra dasgupta, Md Moshiur Rahman, Patanjali SLPSK, and Swarup Bhunia, “Low-overhead Hardware Redaction Using Bitstream Compaction”, GOMACTech Conference, San Diego, CA, USA, May 20-23, 2023.
  • [GOMACTECH’23] Rasheed Almawzan, Reiner Dizon-Paradis, Aritra dasgupta, Dipal Halder, Md Moshiur Rahman, Maneesh Merugu, Sandip Ray, and Swarup Bhunia, “OASIS: A Layered IP Protection Framework for Structured ASIC”, GOMACTech Conference, San Diego, CA, USA, May 20-23, 2023.
  • [GOMACTECH’23] Jackson Fugate, Greg Stitt, Naren vikram Raj Masna, Aritra Dasgupta, and Swarup Bhunia, “ATPG and Test Methods for Redacted IP”, GOMACTech Conference, San Diego, CA, USA, May 20-23, 2023.
  • [GOMACTECH’23] Andrea Ramirez-Salgado, Tanvir Hossain, Tamzidul Hoque, Swarup Bhunia, Mary Koroly, Bradford Davey, Pavlo Antonenko, “Board 265: Engaging Students in Exploring Computer Hardware Fundamentals Using FPGA Board Games”, 2023 ASEE Annual Conference & Exposition, 2023.

2020

  • [GOMACTECH’20] Tamzidul Hoque, Shuo Yang, Aritra Bhattacharya, Jonathan W Cruz, and Swarup Bhunia, “An Automated Framework for Board-level Trojan Benchmarking”, GOMACTech Conference, San Diego, May 16-19, 2020.
  • [GOMACTECH’20] Jonathan W Cruz, Abhishek Nair, Tamzidul Hoque, Prabuddha Chakraborty, Pravin Gaikwad, Naren Masna, and Swarup Bhunia, Brian Dupaix, and Waleed Khalil, “MIMIC: A Machine Intelligence Based Trojan Benchmarking Framework”, GOMACTech Conference, San Diego, May 16-19, 2020.
  • [GOMACTECH’20] Moshiur Rahman, Travis Meade, Yier Jin, and Swarup Bhunia, “You Break I Fix: A Collaborative Approach for Strengthening Sequential Obfuscation of Hardware Intellectual Property”, GOMACTech Conference, San Diego, May 16-19, 2020.
  • [GOMACTECH’20] Chris Taylor, Swarup Bhunia, Brian Dupaix, and Waleed Khalil, “A Structural Analysis of Logic Locking”, GOMACTech Conference, San Diego, May 16-19, 2020.
  • [GLSVLSI’20] Tamzidul Hoque, Patanjali SLPSK, and Swarup Bhunia, “Trust Issues in COTS: The Challenges and Emerging Solutions”, GLSVLSI, Beijing, China, May 2020. [Invited]
  • [ITC’20] Domenic Forte, Swarup Bhunia, Ramesh Karri, Jim Plusquellic and Mark Tehranipoor, “IEEE International Symposium on Hardware Oriented Security and Trust (HOST): Past, Present, and Future”, International Test Conference (ITC), 2020. [Invited]

2019

  • [TECHON’19] Prabuddha Chakraborty and Swarup Bhunia, ” HASTE: Hardware Aware Software Timing Attack Evaluation”, SRC TECHCON, Austin, TX, USA, Sept 2019.
  • [ITC’19] Domenic Forte, Swarup Bhunia, Ramesh Karri, Jim Plusquellic, Mark Tehranipoor, “IEEE International Symposium on Hardware Oriented Security and Trust (HOST): Past, Present, and Future”, to appear in International Test Conference (ITC), Washington DC, Nov 12-14, 2019.
  • [TECHON’19] Atul Prasad Debnath, Swarup Bhunia, and Sandip Ray, “A Flexible Architecture for Systematic Firmware Patching”, SRC TECHCON, Austin, TX, USA, Sept 2019.
  • [VTS’19] Nagmeh Karimi, Jeyavijayan Rajendran, Hassan Salmani, Tamzidul Hoque, and Swarup Bhunia, “Countering IP Security threats in Supply chain”, IEEE VLSI Test Symposium (VTS), April 2019. [Special Session on Hardware IP Security]
  • [DAC’19] Jonathan Cruz, Prabhat Mishra, and Swarup Bhunia, “The Metric Matters: The Art of Measuring Trust in Electronics”, Design Automation Conference (DAC), 2019. [Special Session on “In CAD We Trust? The Question that Drives Trusted Microelectronics”]
  • [ICCE’19] Shuo Yang, Abdulrahman Alaql, Tamzidul Hoque, and Swarup Bhunia, “Runtime Integrity Verification in Cyber-physical Systems Using Side-Channel Fingerprint”, IEEE International Conference on Consumer Electronics (ICCE), Las Vegas, NV, USA, Jan 2019.
  • [GOMACTECH’19] Atul Prasad Debnath, Srivalli Boddupalli, Swarup Bhunia, and Sandip Ray, “ARK: Architecture for Security Resiliency in SoC Designs with NetworK-on-Chip (NoC) Fabrics”, GOMACTech-19 Conference, Albuquerque, NM, 2019.

2018

  • [TECHCON’18] Tamzidul Hoque and Swarup Bhunia, “A Systematic Machine Learning Framework for IP Trust Verification”, SRC TECHCON, Austin, TX, USA, Sept 2018.
  • [GOMACTECH’18] Daniel Capecci, Gustavo Contreras, Domenic Forte, Mark Tehranipoor, and Swarup Bhunia, “Automated SoC Security from Design to Fabrication”, GOMACTech-18 Conference, Miami, Fl, 2018.

2017

  • [GLSVLSI’17] Sarah Amir, Bicky Shakya, Domenic Forte, Mark Tehranipoor, and Swarup Bhunia, “Comparative Analysis of Hardware Obfuscation for IP Protection”, GLSVLSI, Canada, May 2017. [Special Session on “Logic Obfuscation for IoT Security: A New Arms Race?”]
  • [HILTON-HEAD’17] [Abstract & Poster Presentation] Cheng Chen, Swarup Bhunia, Soumyajit Mandal and Fengchao Zhang, “Broadband Quantitative NQR Analysis of Medicines and Nutritional Supplements, Practical Applications of NMR in Industry Conference (PANIC), Hilton Head Island, USA, 2017.
  • [TECHCON’17] Tamzidul Hoque, Prabhat Mishra, and Swarup Bhunia, “A Systemic Feature Extraction Methodology for Machine Learning Based Hardware Trojan Detection”, SRC TECHCON, Austin, TX, USA, Sept 2017.
  • [TECHCON’17] Atul Prasad Debnath, Sandip Ray, and Swarup Bhunia, “An Adaptable System-on-Chip Security Architecture for IoT Applications”, SRC TECHCON, Austin, TX, USA, Sept 2017.

2016

  • [ICCD’16] Sandip Ray, Tamzidul Hoque, Abhishek Basak, and Swarup Bhunia, “The Power Play: Security-Energy Trade-offs in the IoT Regime”, The 34th IEEE International Conference on Computer Design (ICCD), 2016. [Special Session on “Is security the Achilles heel of power-constrained SoCs?”] [Invited]
  • [TECHCON’16] Fengchao Zhang, Abhishek Basak, Sandip Ray, and Swarup Bhunia, “Design-for-Debug Architecture Enhances SoC Security”, SRC TECHCON, Austin, TX, USA, Sept 2016.
  • [TECHCON’16] Robert Karam and Swarup Bhunia, “Energy-Efficient Memory-Centric Reconfigurable Accelerator for Data Intensive Analytics”, SRC TECHCON, Austin, TX, USA, Sept 2016.
  • [TECHCON’16] Tamzidul Hoque, Robert Karam, and Swarup Bhunia, “Protection of IPs Mapped to FPGAs against Malicious Hardware”, SRC TECHCON, Austin, TX, USA, Sept 2016.
  • [VTS’16] Sandip Ray, Swarup Bhunia, Yier Jin, and Mark Tehranipoor, “Security Validation in IoT Space”, IEEE VLSI Test Symposium (VTS), [Special Session on hardware security] [Invited Abstract]
  • [GLSVLSI’16] Robert Karam, Rui Liu, Pai-Yu Chen, Shimeng Yu, and Swarup Bhunia, “Security Primitive Design with Nanoscale Devices: A Case Study with Resistive RAM”, 26th GLSVLSI, Boston, USA, 2016. [Invited]
  • [EUS’16] Robert Karam, Steve Majerus, Swarup Bhunia, Steven Brose, Margot S. Damaser, and Dennis Bourbeau, “Autonomous closed-loop genital nerve stimulation identifies and inhibits hyper-reflexic bladder contractions”, Engineering and Urology Society (EUS) 31st Annual Meeting, 2016. [Abstract]

2015

  • [DAC’15] Sandip Ray, Jin Yang, Abhishek Basak, and Swarup Bhunia, “Correctness and Security and Odds: Post-silicon Validation of Modern SoC Designs”, Design Automation Conference (DAC), 2015. [Invited article in Special Session on “SoC Security Validation”] [Invited]
  • [TECHCON’15] Abhishek Basak, Sandip Ray, and Swarup Bhunia, “A Centralized Flexible Infrastructure for Systematic Implementation of SoC Security Policies”, SRC TECHCON, Austin, TX, USA, Sept 2015.
  • [EUS’15] Irene Makovey, Robert Karam, Steve Majerus, Dennis Bourbeau, Hui Zhu, Swarup Bhunia, Margot S. Damaser, “Event Detection Algorithm in Single Channel Bladder Pressure Recording”, Engineering and Urology Society (EUS) 30th Annual Meeting, 2015. [Abstract]
  • [MWSCAS’15] Robert Karam, Kai Yang, and Swarup Bhunia, “Energy-Efficient Reconfigurable Computing Using Spintronic Memory”, 58th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), 2015, to appear. [Invited article in Special Session on “Emerging Nanoelectronic Logic and Memory Devices based Circuits and Architectures”]
  • [ICM’15] Robert Karam, Dennis Bourbeau, Steve Majerus, Iryna Makovey, Howard B. Goldman, Margot S. Damaser, and Swarup Bhunia, “Real-Time Contraction Event Detection from Bladder Pressure Recordings for Effective Diagnosis and Treatment of Urinary Incontinence”, Innovating for Continence Meeting, Chicago, USA, April 2015.

2014

  • [ACM/SIGDA Newsletter’14] Swarup Bhunia, “What is Hardware Security?”, Vol. 44, No. 12, ACM/SIGDA E-Newsletter, December, 2014.
  • [ICICDT’14] Somnath Paul, Saibal Mukhopadhyay, and Swarup Bhunia, “Robust Low-Power Reconfigurable Computing with a Variation-Aware Preferential Design Approach”, IEEE International Conference on Integrated Circuit Design and Technology (ICICDT), 2014. DOI:1109/ICICDT.2014.6838621 
  • [DATE’14] Swarup Bhunia, Vaishnavi Ranganathan, Tina He, Srihari Rajgopal, Rui Wang, Mehran Mehregany and Philip Feng, “Toward Ultralow-Power Computing at Extreme with Silicon Carbide (SiC) Nanoelectromechanical Logic”, Design Automation and Test in Europe (DATE), 2014. [Invited article in Special Session on “Beyond CMOS Ultra-low-power Computing”] DOI: 7873/DATE2014.246
  • [DATE’14] Somnath Paul, Robert Karam, Swarup Bhunia, and Ruchir Puri, “Energy-Efficient Hardware Acceleration through Computing in the Memory”, in Design Automation and Test in Europe (DATE), 2014. [Invited article in Special Session on “Memcomputing: the Cape of Good Hope”] DOI:7873/DATE2014.279 

2013

  • [MTV’13] Swarup Bhunia and Abhishek Basak, “Secure and Trusted SoC: Challenges and Emerging Solutions”, 14th International Workshop on Microprocessor Test and Verification (MTV), Austin, USA, 2013. [Invited article in Special Session on Security test and verification]
  • [MWSCAS’13] Abhishek Basak, Yu Zheng, Jangwon Park, Jongsun Park, and Swarup Bhunia, “Reconfigurable ECC for Adaptive Protection of Memory”, IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), 2013. [Invited article in special session on Self-Healing and Self-adaptive RF/Mixed-signal circuits for low-cost, high-yield and robust systems]. DOI:1109/MWSCAS.2013.6674841 

2011

  • [ICCD’11] Xinmu Wang, Seetharam Narasimhan, Aswin Krishna, Tatini Mal-Sarkar, and Swarup Bhunia, “Sequential Hardware Trojan Attacks: Experiences from ESC 2010”, 29th IEEE International Conference on Computer Design (ICCD), 2011. [Invited in the special session “Capture the Chip”] DOI: 1109/ICCD.2011.6081413
  • [MWSCAS’11] Hadi Hajimiri, Somnath Paul, Anandaroop Ghosh, Swarup Bhunia, and Prabhat Mishra, “Reliability Improvement in Many-Core Architectures through Computing in Embedded Memory”, IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), 2011. [Invited article in special session on self-healing circuits in scaled technologies]. DOI:1109/MWSCAS.2011.6026672 
  • [TFMN’11] Srihari Rajgopal, Philip X.-L. Feng, Swarup Bhunia and Mehran Mehregany, “Nano Manufacturing of SiC Circuits — Nanomechanical Logic and NEMS-JFET Integration”, Technologies for Future Micro-Nano Manufacturing Workshop, Aug 8-10, 2011. [Invited 2-page abstract]

2010

  • [ASQED’10] Seetharam Narasimhan, Jongsun Park, and Swarup Bhunia, “Digital Signal Processing in Bio-implantable Systems: Design Challenges and Emerging Solutions”, The Asia Symposium on Quality Electronic Design (ASQED), 2010. [Invited paper in special session on bio-sensing and bio-system design].
  • [VTS’10] Swarup Bhunia and Anand Raghunathan, “Hardware Security: Design, Test and Validation Issues”, Hot topic Special Session in IEEE VLSI Test Symposium (VTS), pp. 349-349, 2010. [Invited article on the special session]

2009

  • [HLDVT’09] Rajat Subhra Chakraborty, Seetharam Narasimhan, and Swarup Bhunia, “Hardware Trojan: Threats and Emerging Solutions”, IEEE International High Level Design Validation and Test Workshop (HLDVT), pp. 166-171, 2009. [Invited paper in the special session on post-silicon validation] DOI: 1109/HLDVT.2009.5340158
  • [NANOARCH’09] Somnath Paul and Swarup Bhunia, “Computing with Nanoscale Memory: Model and Architecture,” IEEE/ACM International Symposium on Nanoscale Architecture (NANOARCH), pp. 1-6, 2009. [Invited paper] DOI:1109/NANOARCH.2009.5226362 

2008

  • [ISLPED’08] Swarup Bhunia and Kaushik Roy, “Low Power Design under Parameter Variations”, International Symposium on Low Power Electronics and Design (ISLPED), 2008. [One page article on embedded tutorial] DOI:1109/SOCC.2008.4641552 

2007

  • [ITC’07] Swarup Bhunia and Kaushik Roy, “Power Dissipation, Variations and Nanoscale CMOS Design: Test Challenges and Self-Calibration/Self-Repair Solutions”, International Test Conference (ITC), pp. 1-10, 2007. [Lecture series article] DOI:1109/TEST.2007.4437659 
  • [VLSID’07] Swarup Bhunia, Saibal Mukhopadhyay, and Kaushik Roy, “Process Variations and Process-Tolerant Design”, International Conference on VLSI Design (VLSID), pp. 699-704, 2007. DOI:1109/VLSID.2007.131 

2018

  • VLSI Circuits and Systems Letter (VCAL), official periodical of IEEE Computer Society Technical Committee on VLSI (TCVLSI), “Feature Member” of the Issue, November 2018
  • Foreward in the book “Hardware Security in DSP/Multimedia” by Anirban Sengupta, June 2018.

2016

  • Report from Dagstuhl Seminar 16342, “Foundations of Secure Scaling”, Edited by Lejla Batina, Swarup Bhunia, Patrick Schaumont, and Jean-Pierre Seifert, Dec 2016.

2025

  • Swarup Bhunia and Mark M. Tehranipoor, “Hardware Security: A Hands-on Learning Approach”, Elsevier, Morgan Kaufmann imprint, 2nd Edition, USA, in press, to be published in December 2025.

2018

  • Swarup Bhunia and Mark M. Tehranipoor, “Hardware Security: A Hands-on Learning Approach”, Elsevier, Morgan Kaufmann imprint, 1st Edition, USA, November, 2018.

2017

  • Sandip Ray, Abhishek Basak, and Swarup Bhunia, “Security Policy in System-on-Chip – Specification, Implementation and Verification”, Springer USA, December, 2017.
  • Swarup Bhunia and Mark M. Tehranipoor (Eds.), “The Hardware Trojan War: Attacks, Myths, and Defenses”, Springer, New York, USA, December 2017. [Upcoming]
  • Swarup Bhunia, Sandip Ray, and Susmita Sur-Kolay (Eds.), “Fundamentals of IP and SoC Security: Design, Verification and Debug”, Springer, New York, USA, May 2017.

2016

  • Mark M. Tehranipoor, Domenic Forte, Garrett S. Rose, and Swarup Bhunia (Eds.), “Security Opportunities in Nano Devices and Emerging Technologies”, CRC Press, USA, December 2016.
  • Prabhat Mishra, Swarup Bhunia, and Mark M. Tehranipoor (Eds.), “Hardware IP Security and Trust: Design, Validation, and Test Perspective”, Springer, New York, USA, October 2016.
  • Domenic Forte, Swarup Bhunia, and Mark M. Tehranipoor (Eds.), “Hardware Protection through Obfuscation”, Springer, New York, USA, November 2016.

2014

  • Swarup Bhunia, Steve Majerus, and Mohamad Sawan (Eds.), “Bioimplantable Systems: Design Principles and Applications”, Elsevier, MA, USA, January 2014.

2013

  • Somnath Paul and Swarup Bhunia, “Computing with Memory for Energy-Efficient Robust Systems”, Springer, New York, USA, August 2013.

2010

  • Swarup Bhunia and Saibal Mukhopadhyay (Eds.), “Low-Power Variation-Tolerant Design in Nanometer Silicon”, Springer, New York, USA, 1st Edition, ISBN: 978-1-4419-7417-4, November 2010.

2025

  • Moshiur Rahaman and Swarup Bhunia, “Hardware Obfuscation and Logic Locking”, in Encyclopedia of Cryptography, Security and Privacy, Springer Nature Switzerland, Pages: 1069-1072, 2025.

2020

  • Rajat Shubhra Chakraborty, Pranesh Pranesh Santikellur, and Swarup Bhunia, “Register Transfer Level Hardware Obfuscation”, to appear in the book “Behavioral Synthesis for Hardware Security”, edited by Srinivas Katkoori and Sheikh Ariful Islam, Springer, 2020.
  • Abdulrahman M Alaql, Moshiur Rahman, Tamzidul Hoque, and Swarup Bhunia, “Hardware IP Protection through Obfuscation”, in the book “Frontiers in Hardware Security and Trust”, IET (Institution of Engineering and Technology), edited by Chang Chip Hong (Editor).

2018

  • Atul Prasad Debnath, Tamzidul Hoque, and Swarup Bhunia, “System-on-chip security architecture for internet of things”, in the book “Security and Fault tolerance in Internet of Things”, Springer, 2018, Edited by Rajat Subhra ChakrabortyJimson MathewAthanasios V. Vasilakos.
  • Swarup Bhunia, and Mark Tehranipoor, “Emerging Trend, Industrial Practices, New Attacks”, in the book “The Hardware Trojan War: Attacks, Myths, and Defenses”, Springer, edited by Swarup Bhunia, and Mark Tehranipoor, 2018.
  • Swarup Bhunia, and Mark Tehranipoor, “Hardware Trojan Preliminaries”, in the book “The Hardware Trojan War: Attacks, Myths, and Defenses”, Springer, edited by Swarup Bhunia, and Mark Tehranipoor, 2018.

2017

  • Fahim Rahman, Atul Prasad Deb Nath, Domenic Forte, Swarup Bhunia, and Mark Tehranipoor, “Composition of Physical Unclonable Functions: From Device to Architechture”, in the book “Security Opportunities in Nano Devices and Emerging Technologies”, Springer, edited by Mark Tehranipoor, Domenic Forte, Garrett S. Rose and Swarup Bhunia, December 2017.
  • Fahim Rahman, Atul Prasad Deb Nath, Domenic Forte, Swarup Bhunia, and Mark Tehranipoor, “Nano CMOS Logic-Based Security Primitive Design”, in the book “Security Opportunities in Nano Devices and Emerging Technologies”, Springer, edited by Mark Tehranipoor, Domenic Forte, Garrett S. Rose and Swarup Bhunia, December 2017.
  • Swarup Bhunia, Sandip Ray, and Susmita Sur-Kolay, “SoC Security: Summary and Future Directions”, in the book “Fundamentals of IP and SoC Security: Design, Verification and Debug”, Springer, edited by Swarup Bhunia, Sandip Ray, and Susmita Sur-Kolay, NY, USA, 2017.
  • Swarup Bhunia, Sandip Ray, and Susmita Sur-Kolay, “The Landscape of SoC and IP Security”, in the book “Fundamentals of IP and SoC Security: Design, Verification and Debug”, edited by Swarup Bhunia, Sandip Ray, and Susmita Sur-Kolay, Springer, NY, USA, 2017.

2016

  • Rajat Subhra Chakraborty and Swarup Bhunia, “State Space Obfuscation for Hardware IP Protection”, in the book “Hardware Protection through Obfuscation”, edited by Domenic Forte, Swarup Bhunia, and Mark Tehranipoor, Springer, 2016.
  • Prabhat Mishra, Mark Tehranipoor, and Swarup Bhunia, “Security and Trust Vulnerabilities in Third-party IPs”, in the book “Hardware IP Security and Trust: Design, Validation, and Test Perspective”, edited by Prabhat Mishra, Swarup Bhunia, and Mark Tehranipoor, Springer, 2016.
  • Robert Karam and Swarup Bhunia, “Compute-in-Memory Architecture for Data-Intensive Kernels”, in the book “Emerging Technology and Architecture for Big-data Analytics”, edited by Hao Yu, Chip Hong Chang, and Anupam Chattopadhyay, Springer, 2016.
  • Sandip Ray, Swarup Bhunia, and Prabhat Mishra, “Security Validation in System-on-Chip”, in the book “Fundamentals of IP and SoC Security: Design, Verification, and Debug”, edited by Swarup Bhunia, Sandip Ray, and Susmita Sur-Kolay, Springer, NY, USA, December 2016.

2015

  • Rajat Subhra Chakraborty, Yu Zheng, and Swarup Bhunia, “Obfuscation-based SoC Design for Security against Piracy and Trojan Attacks”, in the book “Secure System Design and Trustable Computing”, edited by Chang Chip Hong and Miodrag Potkonjak, Springer International Publishing AG, Gewerbestrasse 11, 6330 Cham, Switzerland, 2015.
  • Abhishek Basak and Swarup Bhunia, “Implantable Imager for Online Monitoring of Internal Organs”, in the book “Bioimplantable Systems: Design Principles and Applications”, edited by Swarup Bhunia, Steve Majerus, and Mohamad Sawan, Elsevier, MA, USA, February 2015.

2013

  • Abhishek Basak, Vaishnavi Ranganathan, Seetharam Narasimhan, and Swarup Bhunia, “Neural pattern recognition for closed-loop neuro-prosthesis”, in the book “Implantable Bioelectronics – Devices, Materials and Applications”, edited by Evgeny Katz, Wiley-VCH, August 2013.

2012

  • Swarup Bhunia and Seetharam Narasimhan, “Ultralow Power Implantable Electronics”, in the book “Handbook of Energy-Aware and Green Computing”, edited by Sanjay Ranka and Ishfaq Ahmad, Chapman & Hall/CRC Press, January 2012, ISBN: 978-1439850404.

2011

  • Swarup Bhunia and Seetharam Narasimhan, “Hardware Trojan Detection”, in the book “Introduction to Hardware Security and Trust”, edited by Mohammad Tehranipoor and Cliff Wang, Springer, New York, USA, September 2011, ISBN: 978-1441980793.

2009

  • Swarup Bhunia and Kaushik Roy, “Low Power Design Techniques and Test Implications”, in the book “Power-Aware Testing and Test Strategies for Low Power Devices”, edited by Patrick Girard, Nicola Nicolici, and Xiaoqing Wen, Springer, New York, USA, 1st Edition, ISBN: 978-1441909275, August 2009. [Best-seller in International Test Conference 2009].

2024

  • Shivam Bhasin, Anupam Chattopadhyay, Tim Güneysu, Swarup Bhunia: Special Issue on Postquantum Cryptography for Internet of Things. IEEE Des. Test 41(5): 5-6 (2024).

2020

  • Hai Helen Li, Wei Zhang, Swarup Bhunia, Wujie Wen, Introduction to the Special Issue on New Trends in Nanoelectronic Device, Circuit, and Architecture Design, Part 1. ACM J. Emerg. Technol. Comput. Syst. 16(3): 24:1-24:3 (2020).
  • Wei Zhang, Hai Helen Li, Wujie Wen, Swarup Bhunia, Guest Editorial: ACM JETC Special Issue on New Trends in Nanolectronic Device, Circuit, and Architecture Design: Part 2. ACM J. Emerg. Technol. Comput. Syst. 16(4): 35:1-35:3 (2020).

2019

  • Prabhat Mishra, Debdeep Mukhopadhyay, and Swarup Bhunia, “Guest Editorial: Special Section on Autonomous Intelligence for Security and Privacy Analytics”, IEEE Transacations on VLSI (TVLSI), Dec 2019.

2017

  • Swarup Bhunia, An Chen, Ozgur Sinanoglu, and Jason M Fung, “Guest Editors’ Introduction: Security of Beyond-CMOS Devices: Issues and Opportunities”, Journal of Hardware and Systems (TETC), August 2017.
  • Swarup Bhunia and Mark Tehranipoor, “Editorial for the Inaugural Issue of Journal of Hardware and Systems Security (HaSS)”, Journal of Hardware and Systems (HaSS), June 2017.

2016

  • Domenic Forte, Ron Perez, Yongdae Kim, and Swarup Bhunia, “Guest Editors’ Introduction: Supply Chain Security for Cyber-Infrastructure”, IEEE Computer Magazine, 2016.

2015

  • Swarup Bhunia, Jongsun Park, and Sandip Ray, “Guest Editors’ Introduction: Wearables, Implants, and Internet of Things (First Issue)”, IEEE Transactions on Multi-Scale Computing Systems (TMSCS), December 2015.
  • Ramesh Karri, Farinaz Koushanfar, Ozgur Sinanoglu, Yiorgos Makris, Ken Mai, Ahmad Reza Sadeghi, and Swarup Bhunia, “Guest Editorial: Special Section on Hardware Security and Trust”, IEEE Transactions on CAD of Integrated Circuits and Systems (TCAD), June 2015.
  • Saibal Mukhopadhyay, Kaushik Roy, Hillery Hunter, and Swarup Bhunia, “Guest Editorial: Computing in Emerging Technologies (Second Issue)”, IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), March 2015.
  • Swarup Bhunia, Steve Majerus and Mohamad Sawan, “Introduction” in Implantable Biomedical Microsystems: Design Principles and Applications, Elsevier Science and Technology, MA, USA, 1st Edition, ISBN: 0323262082, February 2015.

2014

  • Saibal Mukhopadhyay, Kaushik Roy, Hillery Hunter, and Swarup Bhunia, “Guest Editorial: Computing in Emerging Technologies (First Issue)”, IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), December 2014.

2013

  • Swarup Bhunia, Leyla Nazhandali, and Dakshi Agrawal, “Guest Editors’ Introduction: Trusted System with Untrusted Components: An Emerging Design Need”, IEEE Design & Test of Computers (D&T), April 2013.
  • Somnath Paul and Swarup Bhunia, “Preface” in Computing with Memory for Energy-Efficient Robust Systems, Springer, New York, USA, ISBN: 1461477972, September 2013.

2012

  • Swarup Bhunia and Darrin J. Young, “Introduction to Special Issue on Implantable Electronics”, ACM Journal on Emerging Technologies in Computing Systems (JETC), Vol. 8, No. 2, pp. 7.1-7.2, June 2012.

2010

  • Swarup Bhunia and Rahul Rao, “Guest Editors’ Introduction: Managing Uncertainty through Postfabrication Calibration and Repair”, IEEE Design & Test of Computers (D&T), Vol. 27, No. 6, pp. 4-5, November 2010.
  • Swarup Bhunia and Saibal Mukhopadhyay, “Preface” in Low-Power Variation Tolerant Design in Nanometer Silicon, Springer, New York, USA, 1st Edition, ISBN: 1441974172, November 2010.
  • Swarup Bhunia, “A Special Issue on 23rd IEEE International Conference on VLSI Design, Bangalore, India, 3-7 January 2010”, Journal of Low Power Electronics (JOLPE), Vol. 6, No. 3, pp. 375-375, October 2010.