Dr. Swarup Bhunia is Director of the Nanoscape Research Lab. He is an IEEE Fellow and the Director of the Warren B. Nelms Institute for the Connected World. He holds the titles of Preeminence Professor and Semmoto Endowed Chair Professor of Internet of Things in the Department of Electrical and Computer Engineering at the University of Florida, Gainesville, FL, USA. He received his B.E. (Hons.) from Jadavpur University, Kolkata, India, the M.Tech. degree from the Indian Institute of Technology (IIT), Kharagpur, and his Ph.D. from Purdue University in 2005. Previously, Dr. Bhunia served as the T. and A. Schroeder Associate Professor at Case Western Reserve University and worked in the semiconductor industry on RTL synthesis, verification, and low-power design. He has over 20 years of research and development experience, with over 250 peer-reviewed publications in journals and conferences, more than 10 authored or edited books, and multiple patents. His research focuses on hardware security and trust (including system-on-chip and IoT security), intelligent edge computing, Internet of Things (IoT) technology and applications, low-power and robust design, adaptive nanocomputing, and spectroscopic authentication for food and medicine safety.

Dr. Bhunia’s recognitions include UF Research Foundation Professor (2024), IEEE Fellow (2023), IEEE Hardware Oriented Security and Test (HOST) Hall of Fame (2023), UF Innovator of the Year (2022), HWCOE Doctoral Dissertation Mentoring Award (2022), UF ECE Staff Choice Award for Faculty (2022), IEEE-CS TCVLSI Distinguished Research Award (2018), ECE Research Excellence Award (2018), Research Promotion Initiative Award (2018), Herbert Wertheim Faculty Award for Excellence in Innovation (2018), IBM Faculty Award (2013), NSF CAREER Award (2011), Mike Mesarovic Award for Extraordinary Impact (2011), SRC Technical Excellence Award (2005, team), and SRC Inventor Recognition Award (2009). 

Dr. Bhunia has been serving as founding editor-in-chief in Journal of Hardware and Systems Security (HaSS), an associate editor of IEEE Transactions on CAD (TCAD), IEEE Transactions on Multi-Scale Computing Systems (TMSCS), ACM Journal of Emerging Technologies (JETC), and Journal of Low Power Electronics (JOLPE). He has served as a guest editor of IEEE Design & Test of Computers (2010, 2013), IEEE Computer Magazine (2016), IEEE Transacation on CAD (2015), and IEEE Journal on Emerging and Selected Topics in Circuits and Systems (2014). He has served as co-general chair of the Warren B. Nelms Annual IoT Conference (2024), co-program chair of IEEE IMS3TW 2011, IEEE NANOARCH 2013, IEEE VDAT 2014, and IEEE HOST 2015, and in the technical program committee of Design Automation Conference (2014-2015), Design Automation and Test in Europe (DATE 2006-2010), Hardware Oriented Trust and Security Symposium (HOST 2008-2010), IEEE/IFIP International Conference on VLSI (VLSI SOC 2008), Test Technology Educational Program (TTEP 2006-2008), International Symposium on Low Power Electronics and Design (ISLPED 2007-2008), IEEE/ACM Symposium on Nanoscale Architectures (NANOARCH 2007-2010), IEEE International Conference on VLSI (ISVLSI 2008-2010), International Conference of VLSI Design as a track chair (2010) and in the program committee of International Online Test Symposium (IOLTS 2005). Dr. Bhunia has given tutorials on low-power and robust design and test in premier conference including International Test Conferences (ITC 2009), VLSI Test Symposium (VTS 2010), and Design Automation and Test in Europe (DATE 2009). He is also a distinguished ACM speaker.

[DBLP] [Google Scholar] [Google Patents] [IEEE CEDA CAD-for-Assurance] 

Email: swarup@ece.ufl.edu

Phone: +1-352-392-5989

Office: Malachowsky Hall 4050B, 1889 Museum Rd, Gainesville, FL 32606, USA

• Ph.D.    2000-2005   Purdue University, West Lafayette, IN, USA, Electrical and Computer Engineering
  • Thesis: Power and Yield-Aware Design and Test of Nano-Scale CMOS Circuits
  • Advisor: Dr. Kaushik Roy
  • Dissertation Committee: Kaushik Roy (Chair), Cheng Kok Koh, Khurram Muhammad, and T.N. Vijaykumar

• M.Tech. 1995-1997   Indian Institute of Technology (IIT), Kharagpur, India, Computer Science
  • Thesis: Design and Simulation of an ASIC for Fractal Image Compression
  • Advisor: Dr. Partha Pratim Das  

• B.E. 1991-1995   Jadavpur University, Kolkata, WB, India, Computer Science

Keynote / Distinguished Seminar Series Talks

• Keynote talk at 69^th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), 2026, Cincinnati, OH, USA, August 9–12, 2026 [Upcoming]
• Keynote talk at 2^nd International Symposium on Artificial Intelligence and Internet of Things (AIIOT 2025), Kolkata, India, Dec 22-24, 2025. [Upcoming]
• Keynote Talk at the 7th International Conference on Devices, Circuits and Systems (ISDCS 2025), Kolkata, India, Virtual, 27-30 May 2025.
• Keynote Talk at IC2Tech/CINSER Annual Colloquium on Assured Microelectronics: A National Security Necessity, Chicago State University, Virtual, April 17, 2025.
• Keynote Talk at IEEE 1st IEEE Conference on Secure and Trustworthy CyberInfrastructure for IoT and Microelectronics (SaTC 2025), Dayton, OH, USA, Feb 26, 2025.
• Keynote Talk at the 8th International Embedded Systems Symposium (IESS), Gainesville, Florida, Oct 14-15, 2024.
• Keynote talk at IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Knoxville, Tennesse, July 1-3, 2024.
• Keynote talk at the CAD4SEC workshop, collocated with Design Automation Conference (DAC), 2024.
• Keynote talk at IEEE International Symposium on Electronic Systems Devices and Computing (ESDC), 2024.
• Panelist in SEMI Organized panel on chiplet security, March 14, 2024.
• Webinar at Micro-Electronics Security Training Center (MEST) on New Frontiers in hardware security, Virtual, March 27, 2024.
• Mini Keynote talk at Multicore and Multiprocessor SoCs (MPSoCs) Forum, Montana, US, June 2023.
• Keynote talk at 15th IEEE Dallas Circuits and Systems Conference (DCAS), 2022.
• Keynote talk at International Symposium on Devices, Circuits and Systems (ISDCS), March 2022.
• Keynote talk at IEEE International Symposium on Smart Electronic Systems (iSES) Dec 16, 2020.
• Keynote talk at Silicon Valley Cybersecurity Conference (SVCC), Dec 17, 2020.
• Keynote Talk at IFIP Internet of Things Conference on Innovations in IoT for Solving Global Problems, Oct 31-Nov 1, Tampa, FL, USA, 2019.
• Keynote Talk at Great Lakes Symposium on VLSI (GLSVLSI) on IoT for Solving Global Problems, May 9-11, Washington DC, 2019.
• Visionary Talk at in IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Hong Kong SAR, China, July 9-11, 2018.
• Keynote Talk at 19th International Workshop on Microprocessor/SoC Test, Security & Verification (MTV) on Verification of “Things”: From Microchip to Medicine Austin, TX, USA, December 10-11, 2018.
• Keynote Talk on Hardware Security: Are We Paranoid Enough in IEEE International Conference on Consumer Electronics (ICCE), Las Vegas, USA, January 12-14, 2018.
• Visionary Talk at 2nd IEEE Asian Hardware Oriented Security and Trust Symposium (AsianHOST) Conference, Beijing, China, October 19-20, 2017 (jointly with Prof. Domenic Forte, the talk is delivered by Prof. Forte).
• Distinguished Lecture Series on Cybersecurity talk at University of Kentucky on Emerging Frontiers in Hardware Security, September 11, 2017.
• Distinguished Seminar Series talk at Florida Institute of Technology (FIT) on Emerging Frontiers in Hardware Security, March 23, 2017.
• Keynote Talk on Hardware Security Challenges in Embedded Regime in 6th International Symposium on Embedded computing & system Design (ISED), Patna, India, December 15-17, 2016.
• Keynote Talk on hardware trust verification in the IoT space in The Sixth International Conference on Security, Privacy and Applied Cryptographic Engineering (SPACE), Hyderabad, India, December 16-18, 2016.
• Keynote Talk at 29th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), Sept 19-20, 2016.
• Keynote Talk on hardware security challenges and solutions in the IoT space in IEEE International Verification and Security Workshop (IVSW), Catalunya, Spain, July 4-6, 2016.

E-Workshops

• Semiconductor Research Corporation (SRC) e-workshop on “Infrastructure IP for Security: A Scalable Solution for Secure SoC”, May 26, 2017.
• Semiconductor Research Corporation (SRC) e-workshop on RRAM-based Malleable memory for Energy-Efficient Computing, April 21, 2016.
• Semiconductor Research Corporation (SRC) e-workshop on Infrastructure IP for System-on-Chip (SoC) Security, May 20, 2016.

Other Invited Talks

• Invited Talk at Sandia National Laboratories, The ND Cyber Salon, Nov 5, 2025 (virtual) [Upcoming]
• Invited Talk in 2025 RTX Information Systems and Computing (ISaC) Technology Network (TN) Symposium, April 28 – May 2nd, 2025, Tucson, Arizona
• Invited Talk at National Defense Industrial Association (NDIA) Trust & Assurance Committee (T&AC) Monthly Meeting, Feb 13, 2025, on SENTRY: A Platform to Address Confidentiality, Integrity, and Availability (CIA) in SoC. [Jointly with Dr. Sandip Ray]
• Invited Talk at National Defense Industrial Association (NDIA) Trust & Assurance Committee (T&AC) Monthly Meeting, Feb 13, 2025, on Microelectronics Assurance: Emerging Issues and the Curious Case of AI
• Presentation to JFAC, March 28, 2024, on microelectronics assurance
• Presentation to Analog Devices, May 2, 2024, on SoC security
• Invited talk at Army Research Office (ARO) Workshop, University of Southern California (USC) LA Campus, Sept 23, 2024
• Invited talk to GE Digital, September 28, 2023
• Invited talk at Honeywell on SENTRY Security Engine and MELPUF, October 6, 2023
• Invited talk, Third Musculoskeletal Medicine and Bioengineering Meeting, University of Florida Orthopedics Department, Nov 1, 2023
• Invited talk at Florida Semiconductors Week 2023, Jan 25, 202313.   Invited talk in Duke University workshop on CHIPS Readiness Symposium in AI Hardware/Quantum and Edge Computing, Feb 2023
• Invited talk at KBR on microelectronics assurance, Jan 28, 2022
• Microsoft invited talk on MELPUF, Sept 13, 2022
• Invited talk to Intel SAFE team, Nov 9, 2022
• SCALES Consortium kickoff meeting presentation, Nov 2022
• Invited talk at NIST on OASIS countermeasures jointly with Sandip and JV, July 22, 202219.   Invited talk at IEEE CS San Diego Chapter, August 8, 2022
• IoT an Industry 4.0 Plenary Talk at Jadavpur University, India, Aug 20, 2021
• Graphic Era Dehradun India invited talk on IoT for solving global pro, January 28, 2022
• IEEE DVP-SYP program seminar, Oct 17, 2020
• Invited Distinguished Visitor Program seminar at IEEE Toronto c16 Chapter, Nov 26, 2020
• IEEE Computer Society distinguished lecture, IIT-KGP chapter, Sept 28, 2020
• 5th International Conference on Computer Science and Engineering UBMK invited talk, Sept 9, 2020
• Invited distinguished seminar at University of Buffalo, Nov 20, 2020
• Distinguished lecture at IEEE Computer Society Bangalore Chapter, Dec 12, 2020
• Invited industry talk at Raytheon technologies, Oct 15, 2020
• Invited industry talks at BAE systems, Synopsys, Boeing, 2020
• Invited Talk at the Cyber Physical Security Workshop on IoT Security: New Frontiers, Indian Institute of Technology (IIT), Kharagpur, December 11, 2019.
• Invited talk on CAD for microelectronic assurance at the Quantifiable Assurance for Microelectronics Workshop, organized by OSD (R&E), October 9, 2019, Washington DC.
• Invited Talk at Battelle on CAD for microelectronics Trust, September 19, 2019, Columbus, OH, USA.
• Invited talk at Edaptive Computing, Dayton, OH, USA on CAD for microelectronics Trust, July 17, 2019.
• Invited Talk at Cadence on State space Obfuscation, June 13, 2019, Telecon.
• Invited talk at Special Session at Design Automation Conference (DAC), 2019 on Trust Metric, Las Vegas, NV, USA, June 4-6, 2019.
• Invited talk at MIST Center Industry/University Symposium on Push-Pull Forces on Smart System IoT Hardware, Gainesville, FL, USA, March 29, 2019, on Innovations in IoT for Safe, Secure, Sustainable Society.
• Invited talk at Synopsys on security verification, via Telecon, December 20, 2018.
• Invited talk at IEEE VLSI Test Symposium (VTS), 2019, Monterey, CA, USA, on Hardware IP Protection, April 2019.
• Invited talk in Electrical and Computer Engineering, University of South Florida, November 30, 2018.
• Invited talk at Korea University, Seoul, Korea, on New Frontiers in IoT Security, Aug 21, 2018.
• Invited talk at Kookmin University, Seoul, Korea, on IoT Security and Role of Hardware, Aug 20, 2018.
• Invited talk at University of Sounth Florida (USF), Tampa, Florida, USA. Computer Sceice and Enginering, on Emerging Challenges and Solutions in Hardware Security, September 15, 2018. [Upcoming]
• Invited talk at Draper Lab, on Automatic Fine-Grain Timing Attack Vulnerability Analysis, May 30, 2018.
• Invited talk at Indian Institute of Technology (IIT), Kharagpur, Computer Sceice and Information Technoloyg Department, on IoT Security, December 22, 2017.
• Invited talk at Cisco Research Council, System & Platform Security, San Jose, CAS, USA on New Frontiers in IoT security, December 7, 2017.
• Invited talk at Intel Corporation, Security Research Lab, Portland, OR, USA on hardware for Cyber/Systems Security, July 12, 2017.
• Lecture on hardware and systems security in VLSI Summer School for Undergraduate Students, Indian Institute of Technology (IIT), Kharagpur, India, June 28, 2017.
• Invited talk on DARPA workshop on hardware obfuscation “State Space Obfuscation: The Past and the Prospect”, November 17, 2016.
• Invited talk on “FPGA security in the IoT regime” at Security Center of Excellence (SeCoE), Intel, Portland, OR, USA, Sept 27, 2016.
• Invited talk on “Enemies of IC trust: How to test them?” at special session in International Test Conference (ITC), 2016
• Talk at Dagstuhl Seminar 16342 on hardware security new frontiers, Aug 23, 2016.
• Presentation in IEEE VLSI Test Symposium (VTS) Special Session on IoT Security Architecture, April 25, 2016.
• Talk at Cisco Systems (via WebEx) on Hardware Obfuscation, Feb 4, 2016.
• Talk at IBM, Bangalore, India on infrastructure IP on System-on-Chip (SoC) security, Jan 27, 2016.
• Lunch plenary talk in the FICS Annual Conference on Cybersecurity, Gainesville, FL, on Authentication: from Microchip to Medicine, Feb 9-10, 2016.
• Presentation at 8th IEEE/ACM Workshop on Variability Modeling and Characterization, Austin, TX, USA, on exploiting variability in secure system design, Nov 5, 2015.
• Presentation at International Test Conference (ITC) at Anaheim, CA, USA, on trusted system design with untrusted components, Oct 7, 2015.
• Presentation at EDA Workshop at National Tsing Hua University, Hsinchu, Taiwan, on security issues in PCB and solutions, August 31, 2015.
• Presentation at IBM T J Watson Research Lab, Yorktown Heights, New York, USA, on Data-Intensive Computation with Emerging Memory, May 2015.
• Presentation in Boeing Network & Space Systems, on Hardware IP trust and security, February 17, 2015, Via Telecon
• Presentation in Freescale Semiconductor, on trust issues and solutions in hardware intellectual property (IP), Dec 5, 2014
• Presentation in Army Research Office (ARO) Workshop at NYU-Poly, New York, on infrastructure for system-on-chip security, Nov 12-13, 2014
• Presentation at EDA Workshop, on secure and trustworthy hardware, Daejeon, Korea, on August 26, 2014
• Presentation at Samsung Electronics on new directions in security and energy-efficiency, Su-Won, Korea on August 26, 2014
• Presentation at Pohang University of Science and Technology (POSTECH) on new directions in security and energy-efficiency, Pohang, Korea, on August 27, 2014
• Presentation at Korea University on system-on-chip security, Seoul, Korea, on August 28, 2014
• Presentation in Hathaway Brown High School on Cybersecurity, Shaker Heights, Cleveland, May 15, 2014
• Presentation at Intel University Research Office (URO) workshop on Security Design and Verification, at Portland, OR, USA on Nov 22, 2013
• Presentation at Army Research Office (ARO) Workshop at NYU-Poly, New York, on Supply Chain Risk Mitigation, Nov 12, 2013
• Presentation to Freescale Semiconductor, Austin, TX, USA, on System-on-Chip (SoC) Security, Sept 12, 2013
• Presentation to Intel Corporation, Portland, Microprocessor Research Lab, on memory-centric scalable co-processor (via Telecon), April 5, 2013
• Presentation at University of Florida, Dept. of CISE, on Hardware Security, March 15, 2013
• Presentation at Texas Instruments, Dallas (Microcontroller group) on Energy-Efficient Computing, March 13, 2013
• Presentation at Lockheed Martin, Akron, OH as an guest speaker in the Engineer’s Week celebration, on security of electronics, February 19, 2013
• Presentation to Intel Circuit Research Lab (CRL), Portland, OR, USA on in-memory acceleration, Nov 20, 2012 (via Telecon)
• Presentation in Design and Test Summer School, Oct 25-26, 2012, Puebla, Mexico, organized by National Institute for Astrophysics, Optics, and Electronics, (INAOE), Mexico
• Presentation in Qualcomm Inc., San Diego on Adaptive Computing for Low Power and Variation Tolerance, Aug 2012
• Presentation at IBM TJ Watson Research Lab (New York, USA) on nanocomputing architecture, June 2012
• Presentation at Indian Institute of Technology (IIT), Kharagpur on nanocomputing, Jan 2012
• Presentation at Korea University, Seoul, Korea, on low-power and robust nanoscale architecture, Aug 2011
• Presentation at IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Aug 2011 in special session on self-healing circuits
• Presentation in ARO Special Workshop on Hardware Assurance in Washington DC, Monday, April 11, 2011
• Presentation in IBM Austin Research Lab (ARL), Austin, TX, Monday, Nov 1, 2010
• Presentation at Intel Corporation workshop on external academic research, Portland, OR, USA, Sept 27, 2010
• Presentation at Intel Circuit Research Lab (CRL), on adaptive computing, Portland, OR, USA, Aug 1, 2010
• Presentation at “Apprentice – VTS Edition: Season 3”, Organizer/Moderator: K. S. Kim – Samsung, IEEE VLSI Test Symposium (VTS), 2010
• Presentation at The Asia Symposium on Quality Electronic Design (ASQED) on “Digital Signal Processing in Bio-implantable Systems: Design Challenges and Emerging Solutions”, 2010
• Presentation at IEEE International High Level Design Validation and Test Workshop (HLDVT) on “Hardware Trojan: Threats and Emerging Solutions”, 2009
• Presentation at IEEE International Symposium on Nanoscale Architecture (NANOARCH) on “Computing with Nanoscale Memory: Model and Architecture”, 2009
• Lecture series presentation at International Test Conference (ITC) on “Power Dissipation, Variations and Nanoscale CMOS Design: Test Challenges and Self Calibration/Self Repair Solutions”, Oct 2007
• Presentation at Intel Corporation, Bangalore, India, Jan, 2010
• Presentation at Cryptography Research Institute (CRI), San Francisco, CA, USA, 2009
• Presentation at Intel Corporation, Portland, OR, USA, Feb 2008
• Presentation at LSI Logic on efficient speed binning, Oct 2007
• Presentation to Intel Circuit Research Lab (CRL), Portland, OR, USA, Nov, 2007
• Presentation at Indian Institute of Technology (IIT), Department of Computer Sc., Kharagpur, India, 2006
• IEEE series presentation at Jadavpur University, Department of Electronics & Telecommunications Eng., Kolkata, India, 2006

Other Non-Conference Presentations

• Presentation to delegates of Discover Credit Card on Smart Cart Technology Platform, October 10, 2017.
• Presentation to delegates of Texas Instruments on hardware enabled systems security, September 28, 2017.

Panels

• Panelist at Army Research Office (ARO) Workshop, on “CPS Security”, Sept 23, USC, LA, USA, 2024.
• Panelist at semi.org ESDA webinar, on “Chiplet Security – Current and Future”, March 14, 2024.
• Panelist at IEEE International Conference on Industrial Internet (ICII 2019), on “IoT Security: From Commercial Devices to Industrial Infrastructure”, Nov 11-12, 2019.
• Panelist at IFIP Internet of Things (IFIP-IoT), 2019, on “IoT and AI”, Oct 31 – Nov 1, 2019.
• Panelist in 3^rd Trusted and Assured Microelectronics (TAME) Forum on “Security and Trust Grand Challenges”, November 15, 2018.
• Panelist in IEEE/ACM Great Lakes Symposium on VLSI (GLSVLSI), Chicago, IL, USA, in the panel on “Securing the Systems of the Future – Techniques for a Shifting Attack Space”, May 24, 2018.   
• Panelist in FICS Research Annual Conference, 2018, Gainesville, FL, USA, in the panel on “Platform Security: Challenges and Solutions”, February, 2018.  
• Panelist at the 1^st Trusted and Assured Microelectronics (TAME) Forum on “Need for National Technology Roadmap for Trusted and Assured Microelectronics”, November 29, 2017.
• Panelist at International Test Conference (ITC) on “Automotive Security”, October 30, 2017.
• Panelist at Dagstuhl Seminar 16342 on Foundations of secure scaling: system integration challenges and solutions, Aug 21-26, 2016.
• Panelist in the panel on “DFT vs. Security – Is it a Contradiction? How Can We Get the Best of Both Worlds”, 1st IEEE International Verification and Security Workshop on Hardware Security (IVSW), Catalunya, Spain, July 4-6, 2016.
• Panelist in The 18th ACM/IEEE System Level Interconnect Prediction (SLIP) 2016 Workshop on Hardware Security, Austin, USA, June 5-9, 2016.
• Panelist in the Panel on “Capabilities and Gaps in Systems Security”,  NSF-SRC Secure, Trustworthy, Assured and Resilient Semiconductors and Systems (STARSS) Workshop, San Jose, USA, May 2014.
• Panelist in the Panel on “Teaching Cyber-Security in STEM Curriculums: K though PhD”, 7^th IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), Washington DC, USA, May 2014.
• Panelist in the Panel on “Hackers Not Welcomed – Security Verification Issues”, 14^th International Workshop on Microprocessor Test and Verification (MTV), Austin, USA, December 2013.
• Panelist in the Panel on “CAD for Nanoelectronic Circuit and Architecture – Are we there yet”, 6^th IEEE/ACM International Symposium on Nanoscale Architecture (NANOARCH), June 2010.
• Panelist in the Panel on “Challenges in Hardware Trojan Modeling and Detection”, 3^rd IEEE Hardware Oriented Security and Trust (HOST), June 2010.

Tutorials[Selected through a Peer-Review Process]

• Sandip Ray and Swarup Bhunia, “System-on-Chip Platform Security: Architecture, Implementation, Validation, and Deployment”, IEEE Hardware Oriented Security and Trust (HOST), Washington DC, May 6-10, 2019, Organizer: Swarup Bhunia (U. of Florida). [Half-Day Tutorial]
• Swarup Bhunia, “Hardware Security in the IoT Regime: New Frontiers”, IEEE Custom Integrated Circuits Conference (CICC), Austin, April 14-17, 2019, Organizer: Arijit Chakraborty (Georgia Tech). [Half-Day Tutorial]
• Sandip Ray and Swarup Bhunia, “System-on-Chip Platform Security: Architecture, Implementation, Validation, and Deployment”, IEEE Hardware Oriented Security and Trust (HOST), Washington DC, May 1-4, 2018, Organizer: Swarup Bhunia (U. of Florida). [Half-Day Tutorial]
• Domenic Forte and Swarup Bhunia, “Test Opportunities and Challenges for Secure Hardware and Verifying Trust in Integrated Circuits”, International Test Conference (ITC), Fort Worth, Texas, Nov 15-17, 2016, Organizer: Domenic Forte (U. of Florida). [Half-Day Tutorial]
• Swarup Bhunia, “SECURITY – What are the interactions of hardware faults with system security?”, IEEE International Reliability Physics Symposium (IRPS), Pasadena, CA USA, on, April, 2016. [Embedded Tutorial]
• Swaroop Ghosh, Jaydeep Kulkarni, and Swarup Bhunia, “Embedded Memory Design for Future Technologies: Challenges, Solutions and Applications”, Design Automation and Test in Europe (DATE), Grenoble, France, 2015, Organizer: Swaroop Ghosh (U. of South Florida). [Half-Day Tutorial]
• Prabhat Mishra, Swarup Bhunia and Srivaths Ravi, “Validation and Debug of Security and Trust Issues in Embedded Systems”, 28^th International Conference on VLSI Design, 2015, Organizer: Prabhat Mishra (U. of Florida). [Half-Day Tutorial]
• Patrick Schaumont, Swarup Bhunia, Kazuo Sakiyama, and Makoto Nagata, “Hardware Trust in VLSI Design and Implementations”, Organizer: Kazuo Sakiyama (UEC) and Makoto Nagata (Kobe University), in 20^th Asia South Pacific Design Automation Conference (ASPDAC), Tokyo, Japan, 2015. [Full-Day Tutorial]
• Swarup Bhunia, “Secure and Trustworthy System-on-Chip: Threats and Protections”, in 16^th International Symposium on Quality Electronic Design (ISQED 2015), Organizer: Arijit Raychowdhury (Georgia Tech). [Embedded Tutorial]
• Swarup Bhunia, “Secure and Trusted SoC: Challenges and Emerging Solutions”, in 14^th International Workshop on Microprocessor Test and Verification (MTV), Austin, USA, 2013, Special Session on Security test and verification. [Embedded Tutorial]
• Swarup Bhunia, “The art and Science of Nanomechanical Computing”, in 27^th International Conference on VLSI Design (VLSI-D), 2014, Special Session on “Computing with Post-CMOS Technologies”, Organizer: Kaushik Roy, Purdue University [Embedded Tutorial]
• Swarup Bhunia, “Ultralow Power Computing at Extreme with Silicon Carbide Nanoelectromechanical Logic”, in Design Automation and Test in Europe (DATE), 2014, Special Session on “Beyond CMOS Ultra-low-power Electronics”, Organizer: Saibal Mukhopadhyay, GaTech [Hot Topic Session]
• Swarup Bhunia, “Energy-Efficient Hardware Acceleration through Computing in the Memory”, in Design Automation and Test in Europe (DATE), 2014, Special Session on “Memcomputing: the Cape of Good Hope”, Organizer: Hung-Ming Chen, National Chiao Tung University, Taiwan & Yiyu Shi, Missouri University of Science & Technology [Embedded Tutorial]
• Srivaths Ravi, Anand Ragunathan, Eric Peeters, and Swarup Bhunia, “Designing Secure SoCs”, in 26^th IEEE International Conference on VLSI Design (VLSI-D), 2013. Organizer: Srivaths Ravi, Texas Instruments. [Full-Day Tutorial]
• Susmita Sur-Kolay and Swarup Bhunia, “Intellectual Property Protection and Security in System on a Chip”, in 25^th IEEE International Conference on VLSI Design (VLSI-D), 2012. Organizer: Susmita Sur-Kolay, Indian Statistical Institute. [Full-Day Tutorial]
• Rahul Rao, Saibal Mukhopadhyay, Swarup Bhunia, and Praveen Elakkumanan, “Parameter Variations and Low-Power Design: Test Issues and On-chip Calibration/Repair Solutions”, in International Test Conference (ITC), 2010. Organizer: Rahul Rao, IBM Research. [Full-Day Tutorial]
• Rahul Rao, Saibal Mukhopadhyay, Swarup Bhunia, and Praveen Elakkumanan, “Parameter Variations and Low-Power Design: Test Issues and On-chip Calibration/Repair Solutions”, in VLSI Test Symposium (VTS), 2010. Organizer: Rahul Rao, IBM Research. [Full-Day Tutorial]
• Rahul Rao, Praveen Elakkumanan, Saibal Mukhopadhyay and Swarup Bhunia, “Parametric Failures and Self-Calibration/Self-Repair Solutions”, in International Test Conference (ITC), 2009. Organizer: Saibal Mukhopadhyay, Georgia Tech. [Full-Day Tutorial]
• Swarup Bhunia, Kanak B. Agarwal and Kaushik Roy, “Low Power Design under Parameter Variations”, in Design Automation and Test in Europe (DATE) Conference, 2009. Organizer: Swarup Bhunia, Case Western Reserve U. [Half-Day Tutorial]
• Saibal Mukhopadhyay, Rahul Rao, Praveen Elakkumanan, and Swarup Bhunia, “Parametric Failures and Self-Calibration/Self-Repair Solutions in Nanometer Technologies”, in IEEE International On-Line Test Symposium (IOLTS), 2009. Organizer: Saibal Mukhopadhayay, Georgia Tech. [Full-Day Tutorial]
• Swarup Bhunia, “Variation-Tolerant Low-Power Logic Circuit”, in International Symposium on Quality Electronic Design (ISQED), 2009. Organizer: Rajiv Joshi, IBM Research. [Embedded Tutorial]
• Swarup Bhunia and Kaushik Roy, “Low Power Design under Parameter Variations”, in IEEE International SOC Conference (SOCC), 2008. Organizer: Swarup Bhunia, Case Western Reserve U. [Half-Day Tutorial]
• Kaushik Roy and Swarup Bhunia, “Low Power Design under Parameter Variations”, in International Symposium on Low Power Electronics and Design (ISLPED), 2008. Organizer: Swarup Bhunia, Case Western Reserve U. [Embedded Tutorial]
• Swarup Bhunia and Kaushik Roy, “Process Variations and Process-Tolerant Design”, in International Conference on VLSI Design, Organizer: Swarup Bhunia, Case Western Reserve U. [Embedded Tutorial]