{"id":47,"date":"2024-10-04T20:09:54","date_gmt":"2024-10-04T20:09:54","guid":{"rendered":"https:\/\/sorger.ece.ufl.edu\/?page_id=47"},"modified":"2026-04-08T13:46:57","modified_gmt":"2026-04-08T18:46:57","slug":"research","status":"publish","type":"page","link":"https:\/\/faculty.eng.ufl.edu\/sorger\/research\/","title":{"rendered":"Research"},"content":{"rendered":"\n
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R&D<\/p>

CuttingEdge – Innovative – Realistic<\/p>

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Opto-Electronics<\/h2>

We innovate novel opto-electronic components including Electro Modulators, Photodetectors, Laser\/LEDs, and photonic random access memories (PRAM). We pioneer novel designs using emerging functional materials, device design optimization, prototyping, and chip\/device test and validation.

Applications<\/em><\/span>: optical interconnects, optical transceivers, optical ‘engines’, FPA, compute system








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Photonic-Electronic ASICS<\/h2>

Compute systems are becoming more heterogeneous, including a variety of chip technologies, such as electronic CPU, GPU or neural accelerators, photonic and RF chips and analog\/mixed signal circuits.<\/p><\/span><\/div><\/div>

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Photonic Module Prototyping<\/h2>

AI\/ML application are becoming more demanding. We prototype a variety of ASICs and modules towards improving throughput-power efficiency (TOPS\/W) using ‘best-of-both-worlds’ from photonics and electronics. <\/p><\/span><\/div><\/div><\/div><\/div><\/section><\/div>\n\n\n\n

Advanced Chip Packaging & I\/O <\/h2>

2.5D and 3DHI are poised to improve system performance by 100x [DARPA]. Interposer-less<\/em><\/span> chip packaging concept allow for non-neighbor routing architectures of next-generation AI- and HPC systems. Our research includes interconnects within novel substrates, such as glass, and EMIP-like, optical TSVs, and Fiber-2-die I\/O. <\/p><\/span><\/div><\/div>

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Digital Twins<\/h2>

We believe that the future of semiconductor manufacturing will be driven by digital twins (DT) – digital representation of physical, real-word systems. This includes unit processes in semiconductor fabs, circuits\/devices built, and the manufacturing factory itself. We will utilize ML\/LLM and HiPerGator in addition to data from team members of SMART to advance this next revolution in semiconductor manufacturing. We expect DT’s to accelerate innovation, time-to-market, improve cost and yield, and overall make the domestic semiconductor ecosystem more resilient and economical.

Following the CHIPS DOC\/NIST NOFO for the establishment for the 17th National Manufacturing Institute on ‘Digital Twins for Semiconductor Manufacturing’, we joined the SRC-lead SMART Coalition<\/a> which includes about 150 institutional members nationwide. We will support this by leading the South-East\/Caribbean ‘hub’, if awared. <\/p><\/span><\/div><\/div><\/div><\/div><\/section><\/div>\n\n\n\n

Chips for Space <\/h2>

– Supporting the final Frontier – <\/strong><\/em>

We partner with NASA Langley, Aegis Aerospace, SpaceX and MIT to test our AI photonic chips, photonic wire bonds, and emerging optoelectronic devices, including novel materials at the upcoming MISSE (Materials ISS Experiment #21). The launch with SpaceX in a Falcon Rocket is scheduled for Feb. 2025 here in Florida from Cape Canaveral. Our chips will be placed on 3 different positions on the ISS (i.e. ram, wake, zenith) and exposed to radiation and atomic oxygen amongst enduring thermal cycles. Before & after measurement will reveal any changes to these AI chips and devices. <\/p><\/span><\/div><\/div>

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